55 lines
3.0 KiB
C
55 lines
3.0 KiB
C
/* $NetBSD: jmide_reg.h,v 1.4 2011/10/24 16:06:43 njoly Exp $ */
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/*
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* Copyright (c) 2007 Manuel Bouyer.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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*/
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/* registers definitions for the JMicon JMB36x IDE/SATA controllers */
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#define PCI_JM_CONTROL0 0x40 /* controller control register 0 */
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#define JM_CONTROL0_ROM_EN 0x80000000 /* external ROM enable */
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#define JM_CONTROL0_ID_WR 0x40000000 /* device ID write enable */
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#define JM_CONTROL0_PCIIDE0_MS 0x00800000 /* sata M/S on chan0, PATA0 on chan1 */
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#define JM_CONTROL0_PCIIDE_CS 0x00400000 /* pciide channels swap */
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#define JM_CONTROL0_SATA_PS 0x00200000 /* SATA channel M/S swap */
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#define JM_CONTROL0_AHCI_PS 0x00100000 /* SATA AHCI ports swap */
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#define JM_CONTROL0_SATA1_AHCI 0x00008000 /* SATA port 1 AHCI enable */
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#define JM_CONTROL0_SATA1_IDE 0x00004000 /* SATA port 1 PCIIDE enable */
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#define JM_CONTROL0_SATA0_AHCI 0x00002000 /* SATA port 0 AHCI enable */
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#define JM_CONTROL0_SATA0_IDE 0x00001000 /* SATA port 0 PCIIDE enable */
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#define JM_CONTROL0_AHCI_F1 0x00000200 /* AHCI on function 1 */
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#define JM_CONTROL0_AHCI_EN 0x00000100 /* AHCI enable */
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#define JM_CONTROL0_PATA0_RST 0x00000040 /* PATA port 0 reset */
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#define JM_CONTROL0_PATA0_EN 0x00000020 /* PATA port 0 enable */
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#define JM_CONTROL0_PATA0_SEC 0x00000010 /* PATA 0 enable on secondary chan */
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#define JM_CONTROL0_PATA0_40P 0x00000008 /* PATA 0 40pin cable */
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#define JM_CONTROL0_PCIIDE_F1 0x00000002 /* PCIIDE on function 1 */
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#define JM_CONTROL0_PATA0_PRI 0x00000001 /* PATA 0 enable on primary chan */
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#define PCI_JM_CONTROL1 0x80 /* controller control register 5 */
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#define JM_CONTROL1_PATA1_PRI 0x01000000 /* force PATA 1 on chan0 */
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#define JM_CONTROL1_PATA1_RST 0x00400000 /* PATA 1 reset */
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#define JM_CONTROL1_PATA1_EN 0x00200000 /* PATA 1 enable */
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#define JM_CONTROL1_PATA1_40P 0x00080000 /* PATA 1 40pin cable */
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