471 lines
12 KiB
C
471 lines
12 KiB
C
/* $NetBSD: si.c,v 1.24 1996/03/26 15:01:10 gwr Exp $ */
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/*
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* Copyright (c) 1995 David Jones, Gordon W. Ross
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* Copyright (c) 1994 Adam Glass
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the authors may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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* 4. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by
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* Adam Glass, David Jones, and Gordon Ross
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* This file contains only the machine-dependent parts of the
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* Sun3 SCSI driver. (Autoconfig stuff and DMA functions.)
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* The machine-independent parts are in ncr5380sbc.c
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*
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* Supported hardware includes:
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* Sun SCSI-3 on OBIO (Sun3/50,Sun3/60)
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* Sun SCSI-3 on VME (Sun3/160,Sun3/260)
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*
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* Could be made to support the Sun3/E if someone wanted to.
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*
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* Note: Both supported variants of the Sun SCSI-3 adapter have
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* some really unusual "features" for this driver to deal with,
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* generally related to the DMA engine. The OBIO variant will
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* ignore any attempt to write the FIFO count register while the
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* SCSI bus is in DATA_IN or DATA_OUT phase. This is dealt with
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* by setting the FIFO count early in COMMAND or MSG_IN phase.
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*
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* The VME variant has a bit to enable or disable the DMA engine,
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* but that bit also gates the interrupt line from the NCR5380!
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* Therefore, in order to get any interrupt from the 5380, (i.e.
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* for reselect) one must clear the DMA engine transfer count and
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* then enable DMA. This has the further complication that you
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* CAN NOT touch the NCR5380 while the DMA enable bit is set, so
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* we have to turn DMA back off before we even look at the 5380.
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*
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* What wonderfully whacky hardware this is!
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*
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* Credits, history:
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*
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* David Jones wrote the initial version of this module, which
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* included support for the VME adapter only. (no reselection).
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*
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* Gordon Ross added support for the OBIO adapter, and re-worked
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* both the VME and OBIO code to support disconnect/reselect.
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* (Required figuring out the hardware "features" noted above.)
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*
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* The autoconfiguration boilerplate came from Adam Glass.
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*/
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/errno.h>
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#include <sys/kernel.h>
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#include <sys/malloc.h>
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#include <sys/device.h>
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#include <sys/buf.h>
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#include <sys/proc.h>
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#include <sys/user.h>
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#include <scsi/scsi_all.h>
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#include <scsi/scsi_debug.h>
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#include <scsi/scsiconf.h>
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#include <machine/autoconf.h>
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#include <machine/isr.h>
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#include <machine/obio.h>
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#include <machine/dvma.h>
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#define DEBUG XXX
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#include <dev/ic/ncr5380reg.h>
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#include <dev/ic/ncr5380var.h>
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#include "sireg.h"
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#include "sivar.h"
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int si_debug = 0;
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#ifdef DEBUG
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static int si_link_flags = 0 /* | SDEV_DB2 */ ;
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#endif
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/* How long to wait for DMA before declaring an error. */
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int si_dma_intr_timo = 500; /* ticks (sec. X 100) */
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static void si_minphys __P((struct buf *));
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static int si_print __P((void *, char *));
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static struct scsi_adapter si_ops = {
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ncr5380_scsi_cmd, /* scsi_cmd() */
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si_minphys, /* scsi_minphys() */
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NULL, /* open_target_lu() */
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NULL, /* close_target_lu() */
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};
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/* This is copied from julian's bt driver */
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/* "so we have a default dev struct for our link struct." */
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static struct scsi_device si_dev = {
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NULL, /* Use default error handler. */
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NULL, /* Use default start handler. */
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NULL, /* Use default async handler. */
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NULL, /* Use default "done" routine. */
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};
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/*
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* New-style autoconfig attachment. The cfattach
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* structures are in si_obio.c and si_vme.c
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*/
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struct cfdriver si_cd = {
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NULL, "si", DV_DULL
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};
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void
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si_attach(sc)
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struct si_softc *sc;
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{
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struct ncr5380_softc *ncr_sc = (void *)sc;
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volatile struct si_regs *regs = sc->sc_regs;
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int i;
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/*
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* Fill in the prototype scsi_link.
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*/
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ncr_sc->sc_link.adapter_softc = sc;
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ncr_sc->sc_link.adapter_target = 7;
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ncr_sc->sc_link.adapter = &si_ops;
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ncr_sc->sc_link.device = &si_dev;
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#ifdef DEBUG
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if (si_debug)
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printf("si: Set TheSoftC=%x TheRegs=%x\n", sc, regs);
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ncr_sc->sc_link.flags |= si_link_flags;
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#endif
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/*
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* Initialize fields used by the MI code
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*/
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ncr_sc->sci_r0 = ®s->sci.sci_r0;
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ncr_sc->sci_r1 = ®s->sci.sci_r1;
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ncr_sc->sci_r2 = ®s->sci.sci_r2;
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ncr_sc->sci_r3 = ®s->sci.sci_r3;
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ncr_sc->sci_r4 = ®s->sci.sci_r4;
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ncr_sc->sci_r5 = ®s->sci.sci_r5;
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ncr_sc->sci_r6 = ®s->sci.sci_r6;
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ncr_sc->sci_r7 = ®s->sci.sci_r7;
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/*
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* Allocate DMA handles.
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*/
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i = SCI_OPENINGS * sizeof(struct si_dma_handle);
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sc->sc_dma = (struct si_dma_handle *)
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malloc(i, M_DEVBUF, M_WAITOK);
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if (sc->sc_dma == NULL)
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panic("si: dvma_malloc failed\n");
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for (i = 0; i < SCI_OPENINGS; i++)
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sc->sc_dma[i].dh_flags = 0;
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/*
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* Initialize si board itself.
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*/
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si_reset_adapter(ncr_sc);
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ncr5380_init(ncr_sc);
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ncr5380_reset_scsibus(ncr_sc);
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config_found(&(ncr_sc->sc_dev), &(ncr_sc->sc_link), si_print);
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}
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static int
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si_print(aux, name)
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void *aux;
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char *name;
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{
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if (name != NULL)
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printf("%s: scsibus ", name);
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return UNCONF;
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}
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static void
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si_minphys(struct buf *bp)
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{
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if (bp->b_bcount > MAX_DMA_LEN) {
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#ifdef DEBUG
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if (si_debug) {
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printf("si_minphys len = 0x%x.\n", bp->b_bcount);
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Debugger();
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}
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#endif
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bp->b_bcount = MAX_DMA_LEN;
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}
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return (minphys(bp));
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}
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#define CSR_WANT (SI_CSR_SBC_IP | SI_CSR_DMA_IP | \
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SI_CSR_DMA_CONFLICT | SI_CSR_DMA_BUS_ERR )
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int
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si_intr(void *arg)
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{
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struct si_softc *sc = arg;
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volatile struct si_regs *si = sc->sc_regs;
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int dma_error, claimed;
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u_short csr;
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claimed = 0;
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dma_error = 0;
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/* SBC interrupt? DMA interrupt? */
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csr = si->si_csr;
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NCR_TRACE("si_intr: csr=0x%x\n", csr);
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if (csr & SI_CSR_DMA_CONFLICT) {
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dma_error |= SI_CSR_DMA_CONFLICT;
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printf("si_intr: DMA conflict\n");
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}
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if (csr & SI_CSR_DMA_BUS_ERR) {
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dma_error |= SI_CSR_DMA_BUS_ERR;
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printf("si_intr: DMA bus error\n");
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}
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if (dma_error) {
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if (sc->ncr_sc.sc_state & NCR_DOINGDMA)
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sc->ncr_sc.sc_state |= NCR_ABORTING;
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/* Make sure we will call the main isr. */
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csr |= SI_CSR_DMA_IP;
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}
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if (csr & (SI_CSR_SBC_IP | SI_CSR_DMA_IP)) {
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claimed = ncr5380_intr(&sc->ncr_sc);
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#ifdef DEBUG
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if (!claimed) {
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printf("si_intr: spurious from SBC\n");
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if (si_debug & 4) {
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Debugger(); /* XXX */
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}
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}
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#endif
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}
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return (claimed);
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}
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void
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si_reset_adapter(struct ncr5380_softc *ncr_sc)
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{
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struct si_softc *sc = (struct si_softc *)ncr_sc;
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volatile struct si_regs *si = sc->sc_regs;
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#ifdef DEBUG
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if (si_debug) {
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printf("si_reset_adapter\n");
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}
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#endif
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/*
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* The SCSI3 controller has an 8K FIFO to buffer data between the
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* 5380 and the DMA. Make sure it starts out empty.
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*
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* The reset bits in the CSR are active low.
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*/
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si->si_csr = 0;
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delay(10);
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si->si_csr = SI_CSR_FIFO_RES | SI_CSR_SCSI_RES | SI_CSR_INTR_EN;
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delay(10);
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si->fifo_count = 0;
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if (sc->sc_adapter_type == BUS_VME16) {
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si->dma_addrh = 0;
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si->dma_addrl = 0;
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si->dma_counth = 0;
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si->dma_countl = 0;
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si->si_iv_am = sc->sc_adapter_iv_am;
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si->fifo_cnt_hi = 0;
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}
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SCI_CLR_INTR(ncr_sc);
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}
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/*****************************************************************
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* Common functions for DMA
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****************************************************************/
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/*
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* Allocate a DMA handle and put it in sc->sc_dma. Prepare
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* for DMA transfer. On the Sun3, this means mapping the buffer
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* into DVMA space. dvma_mapin() flushes the cache for us.
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*/
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void
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si_dma_alloc(ncr_sc)
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struct ncr5380_softc *ncr_sc;
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{
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struct si_softc *sc = (struct si_softc *)ncr_sc;
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struct sci_req *sr = ncr_sc->sc_current;
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struct scsi_xfer *xs = sr->sr_xs;
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struct si_dma_handle *dh;
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int i, xlen;
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u_long addr;
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#ifdef DIAGNOSTIC
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if (sr->sr_dma_hand != NULL)
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panic("si_dma_alloc: already have DMA handle");
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#endif
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addr = (u_long) ncr_sc->sc_dataptr;
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xlen = ncr_sc->sc_datalen;
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/* If the DMA start addr is misaligned then do PIO */
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if ((addr & 1) || (xlen & 1)) {
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printf("si_dma_alloc: misaligned.\n");
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return;
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}
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/* Make sure our caller checked sc_min_dma_len. */
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if (xlen < MIN_DMA_LEN)
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panic("si_dma_alloc: xlen=0x%x\n", xlen);
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/*
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* Never attempt single transfers of more than 63k, because
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* our count register may be only 16 bits (an OBIO adapter).
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* This should never happen since already bounded by minphys().
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* XXX - Should just segment these...
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*/
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if (xlen > MAX_DMA_LEN) {
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printf("si_dma_alloc: excessive xlen=0x%x\n", xlen);
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Debugger();
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ncr_sc->sc_datalen = xlen = MAX_DMA_LEN;
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}
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/* Find free DMA handle. Guaranteed to find one since we have
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as many DMA handles as the driver has processes. */
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for (i = 0; i < SCI_OPENINGS; i++) {
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if ((sc->sc_dma[i].dh_flags & SIDH_BUSY) == 0)
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goto found;
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}
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panic("si: no free DMA handles.");
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found:
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dh = &sc->sc_dma[i];
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dh->dh_flags = SIDH_BUSY;
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dh->dh_addr = (u_char*) addr;
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dh->dh_maplen = xlen;
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dh->dh_dvma = 0;
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/* Copy the "write" flag for convenience. */
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if (xs->flags & SCSI_DATA_OUT)
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dh->dh_flags |= SIDH_OUT;
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#if 0
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/*
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* Some machines might not need to remap B_PHYS buffers.
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* The sun3 does not map B_PHYS buffers into DVMA space,
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* (they are mapped into normal KV space) so on the sun3
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* we must always remap to a DVMA address here. Re-map is
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* cheap anyway, because it's done by segments, not pages.
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*/
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if (xs->bp && (xs->bp->b_flags & B_PHYS))
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dh->dh_flags |= SIDH_PHYS;
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#endif
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dh->dh_dvma = (u_long) dvma_mapin((char *)addr, xlen);
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if (!dh->dh_dvma) {
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/* Can't remap segment */
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printf("si_dma_alloc: can't remap %x/%x\n",
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dh->dh_addr, dh->dh_maplen);
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dh->dh_flags = 0;
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return;
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}
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/* success */
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sr->sr_dma_hand = dh;
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return;
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}
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void
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si_dma_free(ncr_sc)
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struct ncr5380_softc *ncr_sc;
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{
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struct sci_req *sr = ncr_sc->sc_current;
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struct si_dma_handle *dh = sr->sr_dma_hand;
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#ifdef DIAGNOSTIC
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if (dh == NULL)
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panic("si_dma_free: no DMA handle");
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#endif
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if (ncr_sc->sc_state & NCR_DOINGDMA)
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panic("si_dma_free: free while in progress");
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if (dh->dh_flags & SIDH_BUSY) {
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/* XXX - Should separate allocation and mapping. */
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/* Give back the DVMA space. */
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dvma_mapout((caddr_t)dh->dh_dvma, dh->dh_maplen);
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dh->dh_dvma = 0;
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dh->dh_flags = 0;
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}
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sr->sr_dma_hand = NULL;
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}
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/*
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* Poll (spin-wait) for DMA completion.
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* Called right after xx_dma_start(), and
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* xx_dma_stop() will be called next.
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* Same for either VME or OBIO.
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*/
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void
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si_dma_poll(ncr_sc)
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struct ncr5380_softc *ncr_sc;
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{
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struct si_softc *sc = (struct si_softc *)ncr_sc;
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struct sci_req *sr = ncr_sc->sc_current;
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struct si_dma_handle *dh = sr->sr_dma_hand;
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volatile struct si_regs *si = sc->sc_regs;
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int tmo, csr_mask;
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/* Make sure DMA started successfully. */
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if (ncr_sc->sc_state & NCR_ABORTING)
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return;
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csr_mask = SI_CSR_SBC_IP | SI_CSR_DMA_IP |
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SI_CSR_DMA_CONFLICT | SI_CSR_DMA_BUS_ERR;
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tmo = 50000; /* X100 = 5 sec. */
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for (;;) {
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if (si->si_csr & csr_mask)
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break;
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if (--tmo <= 0) {
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printf("si: DMA timeout (while polling)\n");
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/* Indicate timeout as MI code would. */
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sr->sr_flags |= SR_OVERDUE;
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break;
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}
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delay(100);
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}
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#ifdef DEBUG
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if (si_debug) {
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printf("si_dma_poll: done, csr=0x%x\n", si->si_csr);
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}
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#endif
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}
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