180 lines
5.3 KiB
C
180 lines
5.3 KiB
C
/* $NetBSD: intr.h,v 1.2 1997/11/27 10:18:47 sakamoto Exp $ */
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/* $OpenBSD: intr.h,v 1.1 1997/10/13 10:53:45 pefo Exp $ */
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/*
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* Copyright (c) 1996, 1997 Charles M. Hannum. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Charles M. Hannum.
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* 4. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _BEBOX_INTR_H_
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#define _BEBOX_INTR_H_
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/* Interrupt priority `levels'. */
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#define IPL_NONE 9 /* nothing */
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#define IPL_SOFTCLOCK 8 /* software clock interrupt */
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#define IPL_SOFTNET 7 /* software network interrupt */
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#define IPL_BIO 6 /* block I/O */
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#define IPL_NET 5 /* network */
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#define IPL_TTY 4 /* terminal */
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#define IPL_IMP 3 /* memory allocation */
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#define IPL_AUDIO 2 /* audio */
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#define IPL_CLOCK 1 /* clock */
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#define IPL_HIGH 0 /* everything */
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#define NIPL 10
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/* Interrupt sharing types. */
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#define IST_NONE 0 /* none */
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#define IST_PULSE 1 /* pulsed */
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#define IST_EDGE 2 /* edge-triggered */
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#define IST_LEVEL 3 /* level-triggered */
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#ifndef _LOCORE
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/*
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* Interrupt handler chains. intr_establish() inserts a handler into
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* the list. The handler is called with its (single) argument.
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*/
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struct intrhand {
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int (*ih_fun) __P((void *));
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void *ih_arg;
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u_long ih_count;
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struct intrhand *ih_next;
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int ih_level;
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int ih_irq;
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};
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void setsoftclock __P((void));
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void clearsoftclock __P((void));
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int splsoftclock __P((void));
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void setsoftnet __P((void));
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void clearsoftnet __P((void));
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int splsoftnet __P((void));
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void do_pending_int __P((void));
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extern volatile int cpl, ipending, astpending, tickspending;
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extern int imask[];
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/*
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* Reorder protection in the following inline functions is
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* achived with the "eieio" instruction which the assembler
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* seems to detect and then doen't move instructions past....
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*/
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static __inline int
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splraise(newcpl)
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int newcpl;
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{
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int oldcpl;
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__asm__ volatile("sync; eieio\n"); /* don't reorder.... */
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oldcpl = cpl;
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cpl = oldcpl | newcpl;
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__asm__ volatile("sync; eieio\n"); /* reorder protect */
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return(oldcpl);
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}
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static __inline void
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splx(newcpl)
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int newcpl;
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{
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__asm__ volatile("sync; eieio\n"); /* reorder protect */
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cpl = newcpl;
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if(ipending & ~newcpl)
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do_pending_int();
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__asm__ volatile("sync; eieio\n"); /* reorder protect */
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}
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static __inline int
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spllower(newcpl)
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int newcpl;
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{
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int oldcpl;
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__asm__ volatile("sync; eieio\n"); /* reorder protect */
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oldcpl = cpl;
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cpl = newcpl;
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if(ipending & ~newcpl)
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do_pending_int();
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__asm__ volatile("sync; eieio\n"); /* reorder protect */
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return(oldcpl);
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}
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/* Following code should be implemented with lwarx/stwcx to avoid
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* the disable/enable. i need to read the manual once more.... */
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static __inline void
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set_sint(pending)
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int pending;
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{
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int msrsave;
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__asm__ ("mfmsr %0" : "=r"(msrsave));
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__asm__ volatile ("mtmsr %0" :: "r"(msrsave & ~PSL_EE));
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ipending |= pending;
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__asm__ volatile ("mtmsr %0" :: "r"(msrsave));
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}
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#define ICU_LEN 32
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#define IRQ_SLAVE 2
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#define LEGAL_IRQ(x) ((x) >= 0 && (x) < ICU_LEN && (x) != IRQ_SLAVE)
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#define MOTHER_BOARD_REG 0x7ffff000
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#define CPU0_INT_MASK 0x0f0
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#define CPU1_INT_MASK 0x1f0
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#define INT_STATE_REG 0x2f0
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#define SINT_CLOCK 0x10000000
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#define SINT_NET 0x20000000
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#define SINT_TTY 0x40000000
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#define SPL_CLOCK 0x80000000
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#define SINT_MASK (SINT_CLOCK|SINT_NET|SINT_TTY)
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#define CNT_SINT_NET 29
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#define CNT_SINT_CLOCK 30
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#define CNT_CLOCK 31
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#define splbio() splraise(imask[IPL_BIO])
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#define splnet() splraise(imask[IPL_NET])
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#define spltty() splraise(imask[IPL_TTY])
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#define splclock() splraise(SPL_CLOCK|SINT_CLOCK|SINT_NET)
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#define splimp() splraise(imask[IPL_IMP])
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#define splstatclock() splhigh()
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#define splsoftclock() spllower(SINT_CLOCK)
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#define splsoftnet() splraise(SINT_NET)
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#define splsofttty() splraise(SINT_TTY)
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#define setsoftclock() set_sint(SINT_CLOCK);
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#define setsoftnet() set_sint(SINT_NET);
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#define setsofttty() set_sint(SINT_TTY);
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#define splhigh() splraise(0xffffffff)
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#define spl0() spllower(0)
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#endif /* !_LOCORE */
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#endif /* !_BEBOX_INTR_H_ */
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