214 lines
6.0 KiB
C
214 lines
6.0 KiB
C
/* $NetBSD: pic_mpcsoc.c,v 1.5 2012/02/01 09:54:03 matt Exp $ */
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/*-
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* Copyright (c) 2007 Michael Lorenz
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: pic_mpcsoc.c,v 1.5 2012/02/01 09:54:03 matt Exp $");
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#include <sys/param.h>
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#include <sys/kmem.h>
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#include <sys/kernel.h>
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#include <uvm/uvm_extern.h>
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#include <machine/pio.h>
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#include <powerpc/openpic.h>
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#include <powerpc/pic/picvar.h>
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#include "opt_interrupt.h"
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static void mpcpic_enable_irq(struct pic_ops *, int, int);
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static void mpcpic_disable_irq(struct pic_ops *, int);
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static void mpcpic_establish_irq(struct pic_ops *, int, int, int);
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static void mpcpic_finish_setup(struct pic_ops *);
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static u_int steer8245[] = {
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0x10200, /* external irq 0 direct/serial */
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0x10220, /* external irq 1 direct/serial */
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0x10240, /* external irq 2 direct/serial */
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0x10260, /* external irq 3 direct/serial */
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0x10280, /* external irq 4 direct/serial */
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0x102a0, /* external irq 5 serial mode */
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0x102c0, /* external irq 6 serial mode */
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0x102e0, /* external irq 7 serial mode */
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0x10300, /* external irq 8 serial mode */
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0x10320, /* external irq 9 serial mode */
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0x10340, /* external irq 10 serial mode */
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0x10360, /* external irq 11 serial mode */
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0x10380, /* external irq 12 serial mode */
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0x103a0, /* external irq 13 serial mode */
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0x103c0, /* external irq 14 serial mode */
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0x103e0, /* external irq 15 serial mode */
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0x11020, /* I2C */
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0x11040, /* DMA 0 */
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0x11060, /* DMA 1 */
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0x110c0, /* MU/I2O */
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0x01120, /* Timer 0 */
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0x01160, /* Timer 1 */
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0x011a0, /* Timer 2 */
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0x011e0, /* Timer 3 */
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0x11120, /* DUART 0, MPC8245 */
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0x11140, /* DUART 1, MPC8245 */
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};
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#define MPCPIC_IVEC(n) (steer8245[(n)])
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#define MPCPIC_IDST(n) (steer8245[(n)] + 0x10)
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static int i8259iswired = 0;
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struct pic_ops *
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setup_mpcpic(void *addr)
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{
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struct openpic_ops *ops;
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struct pic_ops *self;
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int irq;
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u_int x;
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openpic_base = addr;
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ops = kmem_alloc(sizeof(*ops), KM_SLEEP);
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KASSERT(ops != NULL);
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self = &ops->pic;
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x = openpic_read(OPENPIC_FEATURE);
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if (((x & 0x07ff0000) >> 16) == 0)
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panic("setup_mpcpic() called on distributed openpic");
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aprint_normal("OpenPIC Version 1.%d: "
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"Supports %d CPUs and %d interrupt sources.\n",
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x & 0xff, ((x & 0x1f00) >> 8) + 1, ((x & 0x07ff0000) >> 16) + 1);
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#ifdef PIC_I8259
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i8259iswired = 1;
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#endif
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self->pic_numintrs = ((x & 0x07ff0000) >> 16) + 1;
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self->pic_cookie = addr;
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self->pic_enable_irq = mpcpic_enable_irq;
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self->pic_reenable_irq = mpcpic_enable_irq;
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self->pic_disable_irq = mpcpic_disable_irq;
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self->pic_get_irq = opic_get_irq;
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self->pic_ack_irq = opic_ack_irq;
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self->pic_establish_irq = mpcpic_establish_irq;
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self->pic_finish_setup = mpcpic_finish_setup;
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ops->isu = NULL;
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ops->nrofisus = 0; /* internal only */
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ops->flags = 0; /* no flags (yet) */
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ops->irq_per = NULL; /* internal ISU only */
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strcpy(self->pic_name, "mpcpic");
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pic_add(self);
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openpic_set_priority(0, 15);
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for (irq = 0; irq < self->pic_numintrs; irq++) {
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/* make sure to keep disabled */
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openpic_write(MPCPIC_IVEC(irq), OPENPIC_IMASK);
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/* send all interrupts to CPU 0 */
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openpic_write(MPCPIC_IDST(irq), 1 << 0);
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}
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openpic_write(OPENPIC_SPURIOUS_VECTOR, 0xff);
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openpic_set_priority(0, 0);
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/* clear all pending interrunts */
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for (irq = 0; irq < self->pic_numintrs; irq++) {
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openpic_read_irq(0);
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openpic_eoi(0);
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}
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#if 0
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printf("timebase freq=%d\n", openpic_read(0x10f0));
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#endif
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return self;
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}
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void
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mpcpic_reserv16(void)
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{
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extern int max_base; /* intr.c */
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/*
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* reserve 16 irq slot for the case when no i8259 exists to use.
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*/
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max_base += 16;
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}
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static void
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mpcpic_establish_irq(struct pic_ops *pic, int irq, int type, int pri)
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{
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int realpri = max(1, min(15, pri));
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u_int x;
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x = irq;
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x |= OPENPIC_IMASK;
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if ((i8259iswired && irq == 0) ||
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type == IST_EDGE_RISING || type == IST_LEVEL_HIGH)
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x |= OPENPIC_POLARITY_POSITIVE;
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else
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x |= OPENPIC_POLARITY_NEGATIVE;
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if (type == IST_EDGE_FALLING || type == IST_EDGE_RISING)
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x |= OPENPIC_SENSE_EDGE;
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else
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x |= OPENPIC_SENSE_LEVEL;
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x |= realpri << OPENPIC_PRIORITY_SHIFT;
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openpic_write(MPCPIC_IVEC(irq), x);
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aprint_debug("%s: setting IRQ %d to priority %d\n", __func__, irq,
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realpri);
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}
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static void
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mpcpic_enable_irq(struct pic_ops *pic, int irq, int type)
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{
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u_int x;
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x = openpic_read(MPCPIC_IVEC(irq));
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x &= ~OPENPIC_IMASK;
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openpic_write(MPCPIC_IVEC(irq), x);
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}
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static void
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mpcpic_disable_irq(struct pic_ops *pic, int irq)
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{
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u_int x;
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x = openpic_read(MPCPIC_IVEC(irq));
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x |= OPENPIC_IMASK;
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openpic_write(MPCPIC_IVEC(irq), x);
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}
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static void
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mpcpic_finish_setup(struct pic_ops *pic)
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{
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uint32_t cpumask = 1;
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int i;
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for (i = 0; i < pic->pic_numintrs; i++) {
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/* send all interrupts to all active CPUs */
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openpic_write(MPCPIC_IDST(i), cpumask);
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}
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}
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