121 lines
3.7 KiB
C++
121 lines
3.7 KiB
C++
/* -*-C++-*- $NetBSD: arm_mmu.cpp,v 1.6 2008/04/28 20:23:20 martin Exp $ */
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/*-
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* Copyright (c) 2001 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by UCHIYAMA Yasushi.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <arm/arm_mmu.h>
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#include <console.h>
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MemoryManager_ArmMMU::MemoryManager_ArmMMU(Console *&cons,
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size_t pagesize)
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: MemoryManager(cons, pagesize)
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{
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DPRINTF((TEXT("Use ARM software MMU.\n")));
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}
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MemoryManager_ArmMMU::~MemoryManager_ArmMMU(void)
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{
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SetKMode(_kmode);
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}
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BOOL
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MemoryManager_ArmMMU::init(void)
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{
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uint32_t reg;
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_kmode = SetKMode(1);
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// Check system mode
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if ((GetCPSR() & 0x1f) != 0x1f) {
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DPRINTF((TEXT("not System mode\n")));
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return FALSE;
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}
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// Domain access control.(full access)
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SetCop15Reg3(~0);
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// Get Translation table base.
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reg = GetCop15Reg2();
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_table_base = reg & ARM_MMU_TABLEBASE_MASK;
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DPRINTF((TEXT("page directory address=0x%08x->0x%08x(0x%08x)\n"),
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_table_base, readPhysical4(_table_base), reg));
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return TRUE;
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}
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paddr_t
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MemoryManager_ArmMMU::searchPage(vaddr_t vaddr)
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{
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paddr_t daddr, paddr = ~0;
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uint32_t desc1, desc2;
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// set marker.
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memset(LPVOID(vaddr), 0xa5, _page_size);
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// PID virtual address mapping.
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DPRINTF((TEXT("Virtual Address 0x%08x"), vaddr));
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vaddr |= GetCop15Reg13();
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DPRINTF((TEXT("(+PID)-> 0x%08x\n"), vaddr));
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daddr = _table_base | ARM_MMU_TABLEINDEX(vaddr);
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desc1 = readPhysical4(daddr);
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DPRINTF((TEXT("1st level descriptor 0x%08x(addr 0x%08x)\n"),
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desc1, daddr));
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switch(ARM_MMU_LEVEL1DESC_TRANSLATE_TYPE(desc1)) {
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default:
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DPRINTF((TEXT("1st level descriptor fault.\n")));
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break;
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case ARM_MMU_LEVEL1DESC_TRANSLATE_SECTION:
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paddr = ARM_MMU_SECTION_BASE(desc1) |
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ARM_MMU_VADDR_SECTION_INDEX(vaddr);
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DPRINTF((TEXT("section Physical Address 0x%08x\n"), paddr));
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break;
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case ARM_MMU_LEVEL1DESC_TRANSLATE_PAGE:
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DPRINTF((TEXT("-> Level2 page descriptor.\n")));
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daddr = ARM_MMU_PTE_BASE(desc1) |
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ARM_MMU_VADDR_PTE_INDEX(vaddr);
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desc2 = readPhysical4(daddr);
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DPRINTF((TEXT("2nd level descriptor 0x%08x(addr 0x%08x)\n"),
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desc2, daddr));
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switch(desc2 & 0x3) {
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default:
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DPRINTF((TEXT("2nd level descriptor fault.\n")));
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break;
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case 2: // 4Kpage
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paddr =(desc2 & 0xfffff000) |(vaddr & 0x00000fff);
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break;
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case 1: // 64Kpage
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paddr =(desc2 & 0xffff0000) |(vaddr & 0x0000ffff);
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break;
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}
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break;
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}
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return paddr;
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}
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