111 lines
3.3 KiB
ArmAsm
111 lines
3.3 KiB
ArmAsm
/* $NetBSD: cpufunc_asm_arm67.S,v 1.1 2001/11/10 23:14:09 thorpej Exp $ */
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/*
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* Copyright (c) 1997,1998 Mark Brinicombe.
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* Copyright (c) 1997 Causality Limited
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Causality Limited.
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* 4. The name of Causality Limited may not be used to endorse or promote
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* products derived from this software without specific prior written
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* permission.
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*
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* THIS SOFTWARE IS PROVIDED BY CAUSALITY LIMITED ``AS IS'' AND ANY EXPRESS
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* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL CAUSALITY LIMITED BE LIABLE FOR ANY DIRECT,
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* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* ARM6/ARM7 assembly functions for CPU / MMU / TLB specific operations
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*/
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#include <machine/cpu.h>
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#include <machine/asm.h>
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/*
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* Functions to set the MMU Translation Table Base register
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*
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* We need to clean and flush the cache as it uses virtual
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* addresses that are about to change.
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*/
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ENTRY(arm67_setttb)
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mcr p15, 0, r0, c7, c0, 0
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/* Write the TTB */
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mcr p15, 0, r0, c2, c0, 0
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/* If we have updated the TTB we must flush the TLB */
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mcr p15, 0, r0, c5, c0, 0
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/* For good measure we will flush the IDC as well */
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mcr p15, 0, r0, c7, c0, 0
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/* Make sure that pipeline is emptied */
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mov r0, r0
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mov r0, r0
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mov pc, lr
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/*
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* TLB functions
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*/
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ENTRY(arm67_tlb_flush)
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mcr p15, 0, r0, c5, c0, 0
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mov pc, lr
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ENTRY(arm67_tlb_purge)
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mcr p15, 0, r0, c6, c0, 0
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mov pc, lr
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/*
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* Cache functions
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*/
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ENTRY(arm67_cache_flush)
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mcr p15, 0, r0, c7, c0, 0
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mov pc, lr
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/*
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* Context switch.
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*
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* These is the CPU-specific parts of the context switcher cpu_switch()
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* These functions actually perform the TTB reload.
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*
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* NOTE: Special calling convention
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* r1, r4-r13 must be preserved
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*/
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ENTRY(arm67_context_switch)
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/* For good measure we will flush the IDC as well */
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mcr p15, 0, r0, c7, c0, 0 /* flush cache */
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/* Write the TTB */
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mcr p15, 0, r0, c2, c0, 0
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/* If we have updated the TTB we must flush the TLB */
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mcr p15, 0, r0, c5, c0, 0
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#if 0
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/* For good measure we will flush the IDC as well */
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mcr p15, 0, r0, c7, c0, 0 /* flush cache */
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#endif
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/* Make sure that pipeline is emptied */
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mov r0, r0
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mov r0, r0
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mov pc, lr
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