102 lines
3.3 KiB
C
102 lines
3.3 KiB
C
/* $NetBSD: gtreg.h,v 1.4 2006/05/17 17:31:55 tsutsui Exp $ */
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/*
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* Copyright (c) 2003
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* KIYOHARA Takashi. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#define GT_TIMER_COUNTER0 0x850
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#define GT_TIMER_COUNTER1 0x854
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#define GT_TIMER_COUNTER2 0x858
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#define GT_TIMER_COUNTER3 0x85c
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#define GT_TIMER_CTRL 0x864
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#define ENTC0 0x01
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#define TCSEL0 0x02
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#define ENTC1 0x04
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#define TCSEL1 0x08
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#define ENTC2 0x10
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#define TCSEL2 0x20
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#define ENTC3 0x40
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#define TCSEL3 0x80
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#define GT_PCI_COMMAND 0xc00
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#define PCI_BYTESWAP 0x00000001
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#define PCI_SYNCMODE 0x00000006
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#define PCI_PCLK_LOW 0x00000000
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#define PCI_PCLK_HIGH 0x00000002
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#define PCI_PCLK_SYNC 0x00000004
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#define GT_PCI_TIMEOUT_RETRY 0xc04
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#define PCI_TIMEOUT0 0x000000ff
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#define PCI_TIMEOUT1 0x0000ff00
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#define PCI_TIMEOUT1_SHIFT 8
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#define PCI_RETRYCTR 0x00ff0000
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#define PCI_RETRYCTR_SHIFT 16
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#define GT_INTR_CAUSE 0xc18
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#define INTSUM 0x00000001
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#define MEMOUT 0x00000002
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#define DMAOUT 0x00000004
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#define MASTEROUT 0x00000008
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#define DMA0COMP 0x00000010
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#define DMA1COMP 0x00000020
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#define DMA2COMP 0x00000040
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#define DMA3COMP 0x00000080
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#define T0EXP 0x00000100
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#define T1EXP 0x00000200
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#define T2EXP 0x00000400
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#define T3EXP 0x00000800
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#define MASRDERR 0x00001000
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#define SLVWRERR 0x00002000
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#define MASWRERR 0x00004000
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#define SLVRDERR 0x00008000
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#define ADDRERR 0x00010000
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#define MEMERR 0x00020000
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#define MASABORT 0x00040000
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#define TARABORT 0x00080000
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#define RETRYCTR 0x00100000
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#define MASTER_INT0 0x00200000
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#define MASTER_INT1 0x00400000
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#define MASTER_INT2 0x00800000
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#define MASTER_INT3 0x01000000
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#define MASTER_INT4 0x02000000
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#define PCI_INT0 0x04000000
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#define PCI_INT1 0x08000000
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#define PCI_INT2 0x10000000
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#define PCI_INT3 0x20000000
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#define MASTER_INTSUM 0x40000000
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#define PCI_INTSUM 0x80000000
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#define GT_MASTER_MASK 0xc1c
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#define GT_PCI_MASK 0xc24
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#define GT_PCICFG_ADDR 0xcf8
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#define PCICFG_REG 0x000000ff
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#define PCICFG_FUNC 0x00000700
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#define PCICFG_DEV 0x0000f800
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#define PCICFG_BUS 0x00ff0000
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#define PCICFG_ENABLE 0x80000000
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#define GT_PCICFG_DATA 0xcfc
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