140 lines
4.2 KiB
C
140 lines
4.2 KiB
C
/* $NetBSD: dzreg.h,v 1.4 2005/12/11 12:21:20 christos Exp $ */
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/*
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* Copyright (c) 1996 Ken C. Wellsch. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _DEV_DEC_DZREG_H
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#define _DEV_DEC_DZREG_H
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union w_b
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{
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u_short word;
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struct {
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u_char byte_lo;
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u_char byte_hi;
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} bytes;
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};
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struct DZregs
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{
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volatile u_short dz_csr; /* Control/Status Register (R/W) */
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volatile u_short dz_rbuf; /* Receive Buffer (R only) */
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#define dz_lpr dz_rbuf /* Line Parameter Register (W only) */
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volatile union w_b u_tcr; /* Transmit Control Register (R/W) */
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volatile union w_b u_msr; /* Modem Status Register (R only) */
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#define u_tdr u_msr /* Transmit Data Register (W only) */
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};
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#define dz_tcr u_tcr.bytes.byte_lo /* tx enable bits */
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#define dz_dtr u_tcr.bytes.byte_hi /* DTR status bits */
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#define dz_ring u_msr.bytes.byte_lo /* RI status bits */
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#define dz_dcd u_msr.bytes.byte_hi /* DCD status bits */
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#define dz_tbuf u_tdr.bytes.byte_lo /* transmit character */
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#define dz_break u_tdr.bytes.byte_hi /* BREAK set/clr bits */
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typedef struct DZregs dzregs;
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struct dz_regs {
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bus_addr_t dr_csr;
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bus_addr_t dr_rbuf;
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#define dr_lpr dr_rbuf
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bus_addr_t dr_dtr;
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bus_addr_t dr_break;
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bus_addr_t dr_tbuf;
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bus_addr_t dr_tcr;
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bus_addr_t dr_tcrw;
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bus_addr_t dr_ring;
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bus_addr_t dr_dcd;
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bus_addr_t dr_firstreg;
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bus_addr_t dr_winsize;
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};
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#define DZ_UBA_CSR 0
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#define DZ_UBA_RBUF 2
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#define DZ_UBA_DTR 5
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#define DZ_UBA_BREAK 7
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#define DZ_UBA_TBUF 6
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#define DZ_UBA_TCR 4
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#define DZ_UBA_DCD 7
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#define DZ_UBA_RING 6
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#define DZ_UBA_FIRSTREG 0
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#define DZ_UBA_WINSIZE 8
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/* CSR bits */
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#define DZ_CSR_TX_READY 0100000 /* Transmitter Ready */
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#define DZ_CSR_TXIE 0040000 /* Transmitter Interrupt Enable */
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#define DZ_CSR_SA 0020000 /* Silo Alarm */
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#define DZ_CSR_SAE 0010000 /* Silo Alarm Enable */
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#define DZ_CSR_TX_LINE_MASK 0007400 /* Which TX line */
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#define DZ_CSR_RX_DONE 0000200 /* Receiver Done */
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#define DZ_CSR_RXIE 0000100 /* Receiver Interrupt Enable */
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#define DZ_CSR_MSE 0000040 /* Master Scan Enable */
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#define DZ_CSR_RESET 0000020 /* Clear (reset) Controller */
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#define DZ_CSR_MAINTENANCE 0000010
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#define DZ_CSR_UNUSED 0000007
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/* RBUF bits */
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#define DZ_RBUF_DATA_VALID 0100000
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#define DZ_RBUF_OVERRUN_ERR 0040000
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#define DZ_RBUF_FRAMING_ERR 0020000
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#define DZ_RBUF_PARITY_ERR 0010000
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#define DZ_RBUF_RX_LINE_MASK 0007400
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/* LPR bits */
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#define DZ_LPR_UNUSED 0160000
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#define DZ_LPR_RX_ENABLE 0010000
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#define DZ_LPR_B50 0x0
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#define DZ_LPR_B75 0x1
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#define DZ_LPR_B110 0x2
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#define DZ_LPR_B134 0x3
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#define DZ_LPR_B150 0x4
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#define DZ_LPR_B300 0x5
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#define DZ_LPR_B600 0x6
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#define DZ_LPR_B1200 0x7
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#define DZ_LPR_B1800 0x8
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#define DZ_LPR_B2000 0x9
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#define DZ_LPR_B2400 0xA
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#define DZ_LPR_B3600 0xB
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#define DZ_LPR_B4800 0xC
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#define DZ_LPR_B7200 0xD
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#define DZ_LPR_B9600 0xE
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#define DZ_LPR_B19200 0xF
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#define DZ_LPR_OPAR 0000200
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#define DZ_LPR_PARENB 0000100
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#define DZ_LPR_2_STOP 0000040
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#define DZ_LPR_5_BIT_CHAR 0000000
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#define DZ_LPR_6_BIT_CHAR 0000010
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#define DZ_LPR_7_BIT_CHAR 0000020
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#define DZ_LPR_8_BIT_CHAR 0000030
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#define DZ_LPR_CHANNEL_MASK 0000007
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#endif /* _DEV_DEC_DZREG_H */
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