1242 lines
26 KiB
C
1242 lines
26 KiB
C
/* $NetBSD: shpcic.c,v 1.13 2009/08/02 00:06:44 nonaka Exp $ */
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/*
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* Copyright (c) 2005 NONAKA Kimihiro
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: shpcic.c,v 1.13 2009/08/02 00:06:44 nonaka Exp $");
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#include "opt_pci.h"
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#include <sys/device.h>
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#include <sys/extent.h>
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#include <sys/malloc.h>
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#include <dev/pci/pcireg.h>
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#include <dev/pci/pcivar.h>
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#include <dev/pci/pciconf.h>
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#include <dev/pci/pcidevs.h>
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#include <sh3/bscreg.h>
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#include <sh3/cache.h>
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#include <sh3/exception.h>
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#include <sh3/pcicreg.h>
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#include <machine/bus.h>
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#include <machine/intr.h>
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#include <machine/pci_machdep.h>
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#if defined(DEBUG) && !defined(SHPCIC_DEBUG)
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#define SHPCIC_DEBUG 0
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#endif
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#if defined(SHPCIC_DEBUG)
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int shpcic_debug = SHPCIC_DEBUG + 0;
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#define DPRINTF(arg) if (shpcic_debug) printf arg
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#else
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#define DPRINTF(arg)
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#endif
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#define PCI_MODE1_ENABLE 0x80000000UL
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static int shpcic_match(device_t, cfdata_t, void *);
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static void shpcic_attach(device_t, device_t, void *);
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CFATTACH_DECL_NEW(shpcic, 0,
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shpcic_match, shpcic_attach, NULL, NULL);
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/* There can be only one. */
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static int shpcic_found = 0;
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/* PCIC intr priotiry */
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static int shpcic_intr_priority[2] = { IPL_BIO, IPL_BIO };
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static int
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shpcic_match(device_t parent, cfdata_t cf, void *aux)
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{
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pcireg_t id;
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if (shpcic_found)
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return (0);
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switch (cpu_product) {
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case CPU_PRODUCT_7751:
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case CPU_PRODUCT_7751R:
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break;
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default:
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return (0);
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}
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id = _reg_read_4(SH4_PCICONF0);
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switch (PCI_VENDOR(id)) {
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case PCI_VENDOR_HITACHI:
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break;
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default:
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return (0);
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}
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switch (PCI_PRODUCT(id)) {
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case PCI_PRODUCT_HITACHI_SH7751: /* FALLTHROUGH */
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case PCI_PRODUCT_HITACHI_SH7751R:
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break;
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default:
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return (0);
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}
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if (_reg_read_2(SH4_BCR2) & BCR2_PORTEN)
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return (0);
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return (1);
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}
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static void
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shpcic_attach(device_t parent, device_t self, void *aux)
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{
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struct pcibus_attach_args pba;
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#ifdef PCI_NETBSD_CONFIGURE
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struct extent *ioext, *memext;
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#endif
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pcireg_t id, class;
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char devinfo[256];
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shpcic_found = 1;
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aprint_naive("\n");
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id = _reg_read_4(SH4_PCICONF0);
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class = _reg_read_4(SH4_PCICONF2);
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pci_devinfo(id, class, 1, devinfo, sizeof(devinfo));
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aprint_normal(": %s\n", devinfo);
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/* allow PCIC request */
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_reg_write_4(SH4_BCR1, _reg_read_4(SH4_BCR1) | BCR1_BREQEN);
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/* Initialize PCIC */
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_reg_write_4(SH4_PCICR, PCICR_BASE | PCICR_RSTCTL);
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delay(10 * 1000);
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_reg_write_4(SH4_PCICR, PCICR_BASE);
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/* Class: Host-Bridge */
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_reg_write_4(SH4_PCICONF2,
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PCI_CLASS_CODE(PCI_CLASS_BRIDGE, PCI_SUBCLASS_BRIDGE_HOST, 0x00));
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#if !defined(DONT_INIT_PCIBSC)
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#if defined(PCIBCR_BCR1_VAL)
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_reg_write_4(SH4_PCIBCR1, PCIBCR_BCR1_VAL);
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#else
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_reg_write_4(SH4_PCIBCR1, _reg_read_4(SH4_BCR1) | BCR1_MASTER);
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#endif
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#if defined(PCIBCR_BCR2_VAL)
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_reg_write_4(SH4_PCIBCR2, PCIBCR_BCR2_VAL);
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#else
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_reg_write_4(SH4_PCIBCR2, _reg_read_2(SH4_BCR2));
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#endif
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#if defined(SH4) && defined(SH7751R)
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if (cpu_product == CPU_PRODUCT_7751R) {
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#if defined(PCIBCR_BCR3_VAL)
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_reg_write_4(SH4_PCIBCR3, PCIBCR_BCR3_VAL);
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#else
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_reg_write_4(SH4_PCIBCR3, _reg_read_2(SH4_BCR3));
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#endif
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}
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#endif /* SH4 && SH7751R && PCIBCR_BCR3_VAL */
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#if defined(PCIBCR_WCR1_VAL)
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_reg_write_4(SH4_PCIWCR1, PCIBCR_WCR1_VAL);
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#else
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_reg_write_4(SH4_PCIWCR1, _reg_read_4(SH4_WCR1));
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#endif
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#if defined(PCIBCR_WCR2_VAL)
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_reg_write_4(SH4_PCIWCR2, PCIBCR_WCR2_VAL);
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#else
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_reg_write_4(SH4_PCIWCR2, _reg_read_4(SH4_WCR2));
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#endif
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#if defined(PCIBCR_WCR3_VAL)
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_reg_write_4(SH4_PCIWCR3, PCIBCR_WCR3_VAL);
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#else
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_reg_write_4(SH4_PCIWCR3, _reg_read_4(SH4_WCR3));
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#endif
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#if defined(PCIBCR_MCR_VAL)
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_reg_write_4(SH4_PCIMCR, PCIBCR_MCR_VAL);
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#else
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_reg_write_4(SH4_PCIMCR, _reg_read_4(SH4_MCR));
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#endif
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#endif /* !DONT_INIT_PCIBSC */
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/* set PCI I/O, memory base address */
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_reg_write_4(SH4_PCIIOBR, SH4_PCIC_IO);
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_reg_write_4(SH4_PCIMBR, SH4_PCIC_MEM);
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/* set PCI local address 0 */
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_reg_write_4(SH4_PCILSR0, (64 - 1) << 20);
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_reg_write_4(SH4_PCILAR0, 0xac000000);
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_reg_write_4(SH4_PCICONF5, 0xac000000);
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/* set PCI local address 1 */
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_reg_write_4(SH4_PCILSR1, (64 - 1) << 20);
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_reg_write_4(SH4_PCILAR1, 0xac000000);
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_reg_write_4(SH4_PCICONF6, 0x8c000000);
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/* Enable I/O, memory, bus-master */
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_reg_write_4(SH4_PCICONF1, PCI_COMMAND_IO_ENABLE
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| PCI_COMMAND_MEM_ENABLE
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| PCI_COMMAND_MASTER_ENABLE
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| PCI_COMMAND_STEPPING_ENABLE
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| PCI_STATUS_DEVSEL_MEDIUM);
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/* Initialize done. */
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_reg_write_4(SH4_PCICR, PCICR_BASE | PCICR_CFINIT);
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/* set PCI controller interrupt priority */
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intpri_intr_priority(SH4_INTEVT_PCIERR, shpcic_intr_priority[0]);
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intpri_intr_priority(SH4_INTEVT_PCISERR, shpcic_intr_priority[1]);
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/* PCI bus */
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#ifdef PCI_NETBSD_CONFIGURE
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ioext = extent_create("pciio",
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SH4_PCIC_IO, SH4_PCIC_IO + SH4_PCIC_IO_SIZE - 1,
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M_DEVBUF, NULL, 0, EX_NOWAIT);
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memext = extent_create("pcimem",
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SH4_PCIC_MEM, SH4_PCIC_MEM + SH4_PCIC_MEM_SIZE - 1,
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M_DEVBUF, NULL, 0, EX_NOWAIT);
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pci_configure_bus(NULL, ioext, memext, NULL, 0, sh_cache_line_size);
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extent_destroy(ioext);
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extent_destroy(memext);
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#endif
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/* PCI bus */
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memset(&pba, 0, sizeof(pba));
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pba.pba_iot = shpcic_get_bus_io_tag();
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pba.pba_memt = shpcic_get_bus_mem_tag();
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pba.pba_dmat = shpcic_get_bus_dma_tag();
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pba.pba_dmat64 = NULL;
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pba.pba_pc = NULL;
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pba.pba_bus = 0;
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pba.pba_bridgetag = NULL;
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pba.pba_flags = PCI_FLAGS_IO_ENABLED | PCI_FLAGS_MEM_ENABLED;
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config_found(self, &pba, NULL);
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}
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int
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shpcic_bus_maxdevs(void *v, int busno)
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{
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/*
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* Bus number is irrelevant. Configuration Mechanism 1 is in
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* use, can have devices 0-32 (i.e. the `normal' range).
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*/
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return (32);
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}
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pcitag_t
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shpcic_make_tag(void *v, int bus, int device, int function)
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{
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pcitag_t tag;
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if (bus >= 256 || device >= 32 || function >= 8)
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panic("pci_make_tag: bad request");
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tag = PCI_MODE1_ENABLE |
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(bus << 16) | (device << 11) | (function << 8);
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return (tag);
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}
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void
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shpcic_decompose_tag(void *v, pcitag_t tag, int *bp, int *dp, int *fp)
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{
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if (bp != NULL)
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*bp = (tag >> 16) & 0xff;
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if (dp != NULL)
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*dp = (tag >> 11) & 0x1f;
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if (fp != NULL)
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*fp = (tag >> 8) & 0x7;
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}
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pcireg_t
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shpcic_conf_read(void *v, pcitag_t tag, int reg)
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{
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pcireg_t data;
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int s;
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s = splhigh();
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_reg_write_4(SH4_PCIPAR, tag | reg);
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data = _reg_read_4(SH4_PCIPDR);
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_reg_write_4(SH4_PCIPAR, 0);
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splx(s);
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return data;
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}
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void
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shpcic_conf_write(void *v, pcitag_t tag, int reg, pcireg_t data)
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{
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int s;
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s = splhigh();
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_reg_write_4(SH4_PCIPAR, tag | reg);
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_reg_write_4(SH4_PCIPDR, data);
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_reg_write_4(SH4_PCIPAR, 0);
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splx(s);
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}
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int
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shpcic_set_intr_priority(int intr, int level)
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{
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int evtcode;
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if ((intr != 0) && (intr != 1)) {
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return (-1);
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}
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if ((level < IPL_NONE) || (level > IPL_HIGH)) {
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return (-1);
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}
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if (intr == 0) {
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evtcode = SH4_INTEVT_PCIERR;
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} else {
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evtcode = SH4_INTEVT_PCISERR;
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}
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intpri_intr_priority(evtcode, shpcic_intr_priority[intr]);
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shpcic_intr_priority[intr] = level;
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return (0);
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}
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void *
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shpcic_intr_establish(int evtcode, int (*ih_func)(void *), void *ih_arg)
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{
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int level;
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switch (evtcode) {
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case SH4_INTEVT_PCISERR:
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level = shpcic_intr_priority[1];
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break;
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case SH4_INTEVT_PCIDMA3:
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case SH4_INTEVT_PCIDMA2:
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case SH4_INTEVT_PCIDMA1:
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case SH4_INTEVT_PCIDMA0:
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case SH4_INTEVT_PCIPWON:
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case SH4_INTEVT_PCIPWDWN:
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case SH4_INTEVT_PCIERR:
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level = shpcic_intr_priority[0];
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break;
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default:
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printf("shpcic_intr_establish: unknown evtcode = 0x%08x\n",
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evtcode);
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return NULL;
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}
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return intc_intr_establish(evtcode, IST_LEVEL, level, ih_func, ih_arg);
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}
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void
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shpcic_intr_disestablish(void *ih)
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{
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intc_intr_disestablish(ih);
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}
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/*
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* shpcic bus space
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*/
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int
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shpcic_iomem_map(void *v, bus_addr_t bpa, bus_size_t size,
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int flags, bus_space_handle_t *bshp)
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{
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*bshp = (bus_space_handle_t)bpa;
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return (0);
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}
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void
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shpcic_iomem_unmap(void *v, bus_space_handle_t bsh, bus_size_t size)
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{
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/* Nothing to do */
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}
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int
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shpcic_iomem_subregion(void *v, bus_space_handle_t bsh,
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bus_size_t offset, bus_size_t size, bus_space_handle_t *nbshp)
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{
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*nbshp = bsh + offset;
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return (0);
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}
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int
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shpcic_iomem_alloc(void *v, bus_addr_t rstart, bus_addr_t rend,
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bus_size_t size, bus_size_t alignment, bus_size_t boundary, int flags,
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bus_addr_t *bpap, bus_space_handle_t *bshp)
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{
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*bshp = *bpap = rstart;
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return (0);
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}
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void
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shpcic_iomem_free(void *v, bus_space_handle_t bsh, bus_size_t size)
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{
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/* Nothing to do */
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}
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paddr_t
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shpcic_iomem_mmap(void *v, bus_addr_t addr, off_t off, int prot, int flags)
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{
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return (paddr_t)-1;
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}
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/*
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* shpcic bus space io/mem read/write
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*/
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/* read */
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static inline uint8_t __shpcic_io_read_1(bus_space_handle_t bsh,
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bus_size_t offset);
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static inline uint16_t __shpcic_io_read_2(bus_space_handle_t bsh,
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bus_size_t offset);
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static inline uint32_t __shpcic_io_read_4(bus_space_handle_t bsh,
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bus_size_t offset);
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static inline uint8_t __shpcic_mem_read_1(bus_space_handle_t bsh,
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bus_size_t offset);
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static inline uint16_t __shpcic_mem_read_2(bus_space_handle_t bsh,
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bus_size_t offset);
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static inline uint32_t __shpcic_mem_read_4(bus_space_handle_t bsh,
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bus_size_t offset);
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static inline uint8_t
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__shpcic_io_read_1(bus_space_handle_t bsh, bus_size_t offset)
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{
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u_long adr = (u_long)(bsh + offset) & SH4_PCIC_IO_MASK;
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return *(volatile uint8_t *)(SH4_PCIC_IO + adr);
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}
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static inline uint16_t
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__shpcic_io_read_2(bus_space_handle_t bsh, bus_size_t offset)
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{
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u_long adr = (u_long)(bsh + offset) & SH4_PCIC_IO_MASK;
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return *(volatile uint16_t *)(SH4_PCIC_IO + adr);
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}
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static inline uint32_t
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__shpcic_io_read_4(bus_space_handle_t bsh, bus_size_t offset)
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{
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u_long adr = (u_long)(bsh + offset) & SH4_PCIC_IO_MASK;
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return *(volatile uint32_t *)(SH4_PCIC_IO + adr);
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}
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static inline uint8_t
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__shpcic_mem_read_1(bus_space_handle_t bsh, bus_size_t offset)
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{
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u_long adr = (u_long)(bsh + offset) & SH4_PCIC_MEM_MASK;
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return *(volatile uint8_t *)(SH4_PCIC_MEM + adr);
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}
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static inline uint16_t
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__shpcic_mem_read_2(bus_space_handle_t bsh, bus_size_t offset)
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{
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u_long adr = (u_long)(bsh + offset) & SH4_PCIC_MEM_MASK;
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return *(volatile uint16_t *)(SH4_PCIC_MEM + adr);
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}
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static inline uint32_t
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__shpcic_mem_read_4(bus_space_handle_t bsh, bus_size_t offset)
|
|
{
|
|
u_long adr = (u_long)(bsh + offset) & SH4_PCIC_MEM_MASK;
|
|
|
|
return *(volatile uint32_t *)(SH4_PCIC_MEM + adr);
|
|
}
|
|
|
|
/*
|
|
* read single
|
|
*/
|
|
uint8_t
|
|
shpcic_io_read_1(void *v, bus_space_handle_t bsh, bus_size_t offset)
|
|
{
|
|
uint8_t value;
|
|
|
|
value = __shpcic_io_read_1(bsh, offset);
|
|
|
|
return value;
|
|
}
|
|
|
|
uint16_t
|
|
shpcic_io_read_2(void *v, bus_space_handle_t bsh, bus_size_t offset)
|
|
{
|
|
uint16_t value;
|
|
|
|
value = __shpcic_io_read_2(bsh, offset);
|
|
|
|
return value;
|
|
}
|
|
|
|
uint32_t
|
|
shpcic_io_read_4(void *v, bus_space_handle_t bsh, bus_size_t offset)
|
|
{
|
|
uint32_t value;
|
|
|
|
value = __shpcic_io_read_4(bsh, offset);
|
|
|
|
return value;
|
|
}
|
|
|
|
uint8_t
|
|
shpcic_mem_read_1(void *v, bus_space_handle_t bsh, bus_size_t offset)
|
|
{
|
|
uint8_t value;
|
|
|
|
value = __shpcic_mem_read_1(bsh, offset);
|
|
|
|
return value;
|
|
}
|
|
|
|
uint16_t
|
|
shpcic_mem_read_2(void *v, bus_space_handle_t bsh, bus_size_t offset)
|
|
{
|
|
uint16_t value;
|
|
|
|
value = __shpcic_mem_read_2(bsh, offset);
|
|
|
|
return value;
|
|
}
|
|
|
|
uint32_t
|
|
shpcic_mem_read_4(void *v, bus_space_handle_t bsh, bus_size_t offset)
|
|
{
|
|
uint32_t value;
|
|
|
|
value = __shpcic_mem_read_4(bsh, offset);
|
|
|
|
return value;
|
|
}
|
|
|
|
/*
|
|
* read multi
|
|
*/
|
|
void
|
|
shpcic_io_read_multi_1(void *v, bus_space_handle_t bsh,
|
|
bus_size_t offset, uint8_t *addr, bus_size_t count)
|
|
{
|
|
|
|
while (count--) {
|
|
*addr++ = __shpcic_io_read_1(bsh, offset);
|
|
}
|
|
}
|
|
|
|
void
|
|
shpcic_io_read_multi_2(void *v, bus_space_handle_t bsh,
|
|
bus_size_t offset, uint16_t *addr, bus_size_t count)
|
|
{
|
|
|
|
while (count--) {
|
|
*addr++ = __shpcic_io_read_2(bsh, offset);
|
|
}
|
|
}
|
|
|
|
void
|
|
shpcic_io_read_multi_4(void *v, bus_space_handle_t bsh,
|
|
bus_size_t offset, uint32_t *addr, bus_size_t count)
|
|
{
|
|
|
|
while (count--) {
|
|
*addr++ = __shpcic_io_read_4(bsh, offset);
|
|
}
|
|
}
|
|
|
|
void
|
|
shpcic_mem_read_multi_1(void *v, bus_space_handle_t bsh,
|
|
bus_size_t offset, uint8_t *addr, bus_size_t count)
|
|
{
|
|
|
|
while (count--) {
|
|
*addr++ = __shpcic_mem_read_1(bsh, offset);
|
|
}
|
|
}
|
|
|
|
void
|
|
shpcic_mem_read_multi_2(void *v, bus_space_handle_t bsh,
|
|
bus_size_t offset, uint16_t *addr, bus_size_t count)
|
|
{
|
|
|
|
while (count--) {
|
|
*addr++ = __shpcic_mem_read_2(bsh, offset);
|
|
}
|
|
}
|
|
|
|
void
|
|
shpcic_mem_read_multi_4(void *v, bus_space_handle_t bsh,
|
|
bus_size_t offset, uint32_t *addr, bus_size_t count)
|
|
{
|
|
|
|
while (count--) {
|
|
*addr++ = __shpcic_mem_read_4(bsh, offset);
|
|
}
|
|
}
|
|
|
|
/*
|
|
*
|
|
* read region
|
|
*/
|
|
void
|
|
shpcic_io_read_region_1(void *v, bus_space_handle_t bsh,
|
|
bus_size_t offset, uint8_t *addr, bus_size_t count)
|
|
{
|
|
|
|
while (count--) {
|
|
*addr++ = __shpcic_io_read_1(bsh, offset);
|
|
offset += 1;
|
|
}
|
|
}
|
|
|
|
void
|
|
shpcic_io_read_region_2(void *v, bus_space_handle_t bsh,
|
|
bus_size_t offset, uint16_t *addr, bus_size_t count)
|
|
{
|
|
|
|
while (count--) {
|
|
*addr++ = __shpcic_io_read_2(bsh, offset);
|
|
offset += 2;
|
|
}
|
|
}
|
|
|
|
void
|
|
shpcic_io_read_region_4(void *v, bus_space_handle_t bsh,
|
|
bus_size_t offset, uint32_t *addr, bus_size_t count)
|
|
{
|
|
|
|
while (count--) {
|
|
*addr++ = __shpcic_io_read_4(bsh, offset);
|
|
offset += 4;
|
|
}
|
|
}
|
|
|
|
void
|
|
shpcic_mem_read_region_1(void *v, bus_space_handle_t bsh,
|
|
bus_size_t offset, uint8_t *addr, bus_size_t count)
|
|
{
|
|
|
|
while (count--) {
|
|
*addr++ = __shpcic_mem_read_1(bsh, offset);
|
|
offset += 1;
|
|
}
|
|
}
|
|
|
|
void
|
|
shpcic_mem_read_region_2(void *v, bus_space_handle_t bsh,
|
|
bus_size_t offset, uint16_t *addr, bus_size_t count)
|
|
{
|
|
|
|
while (count--) {
|
|
*addr++ = __shpcic_mem_read_2(bsh, offset);
|
|
offset += 2;
|
|
}
|
|
}
|
|
|
|
void
|
|
shpcic_mem_read_region_4(void *v, bus_space_handle_t bsh,
|
|
bus_size_t offset, uint32_t *addr, bus_size_t count)
|
|
{
|
|
|
|
while (count--) {
|
|
*addr++ = __shpcic_mem_read_4(bsh, offset);
|
|
offset += 4;
|
|
}
|
|
}
|
|
|
|
/* write */
|
|
static inline void __shpcic_io_write_1(bus_space_handle_t bsh,
|
|
bus_size_t offset, uint8_t value);
|
|
static inline void __shpcic_io_write_2(bus_space_handle_t bsh,
|
|
bus_size_t offset, uint16_t value);
|
|
static inline void __shpcic_io_write_4(bus_space_handle_t bsh,
|
|
bus_size_t offset, uint32_t value);
|
|
static inline void __shpcic_mem_write_1(bus_space_handle_t bsh,
|
|
bus_size_t offset, uint8_t value);
|
|
static inline void __shpcic_mem_write_2(bus_space_handle_t bsh,
|
|
bus_size_t offset, uint16_t value);
|
|
static inline void __shpcic_mem_write_4(bus_space_handle_t bsh,
|
|
bus_size_t offset, uint32_t value);
|
|
|
|
static inline void
|
|
__shpcic_io_write_1(bus_space_handle_t bsh, bus_size_t offset,
|
|
uint8_t value)
|
|
{
|
|
u_long adr = (u_long)(bsh + offset) & SH4_PCIC_IO_MASK;
|
|
|
|
*(volatile uint8_t *)(SH4_PCIC_IO + adr) = value;
|
|
}
|
|
|
|
static inline void
|
|
__shpcic_io_write_2(bus_space_handle_t bsh, bus_size_t offset,
|
|
uint16_t value)
|
|
{
|
|
u_long adr = (u_long)(bsh + offset) & SH4_PCIC_IO_MASK;
|
|
|
|
*(volatile uint16_t *)(SH4_PCIC_IO + adr) = value;
|
|
}
|
|
|
|
static inline void
|
|
__shpcic_io_write_4(bus_space_handle_t bsh, bus_size_t offset,
|
|
uint32_t value)
|
|
{
|
|
u_long adr = (u_long)(bsh + offset) & SH4_PCIC_IO_MASK;
|
|
|
|
*(volatile uint32_t *)(SH4_PCIC_IO + adr) = value;
|
|
}
|
|
|
|
static inline void
|
|
__shpcic_mem_write_1(bus_space_handle_t bsh, bus_size_t offset,
|
|
uint8_t value)
|
|
{
|
|
u_long adr = (u_long)(bsh + offset) & SH4_PCIC_MEM_MASK;
|
|
|
|
*(volatile uint8_t *)(SH4_PCIC_MEM + adr) = value;
|
|
}
|
|
|
|
static inline void
|
|
__shpcic_mem_write_2(bus_space_handle_t bsh, bus_size_t offset,
|
|
uint16_t value)
|
|
{
|
|
u_long adr = (u_long)(bsh + offset) & SH4_PCIC_MEM_MASK;
|
|
|
|
*(volatile uint16_t *)(SH4_PCIC_MEM + adr) = value;
|
|
}
|
|
|
|
static inline void
|
|
__shpcic_mem_write_4(bus_space_handle_t bsh, bus_size_t offset,
|
|
uint32_t value)
|
|
{
|
|
u_long adr = (u_long)(bsh + offset) & SH4_PCIC_MEM_MASK;
|
|
|
|
*(volatile uint32_t *)(SH4_PCIC_MEM + adr) = value;
|
|
}
|
|
|
|
/*
|
|
* write single
|
|
*/
|
|
void
|
|
shpcic_io_write_1(void *v, bus_space_handle_t bsh,
|
|
bus_size_t offset, uint8_t value)
|
|
{
|
|
|
|
__shpcic_io_write_1(bsh, offset, value);
|
|
}
|
|
|
|
void
|
|
shpcic_io_write_2(void *v, bus_space_handle_t bsh,
|
|
bus_size_t offset, uint16_t value)
|
|
{
|
|
|
|
__shpcic_io_write_2(bsh, offset, value);
|
|
}
|
|
|
|
void
|
|
shpcic_io_write_4(void *v, bus_space_handle_t bsh,
|
|
bus_size_t offset, uint32_t value)
|
|
{
|
|
|
|
__shpcic_io_write_4(bsh, offset, value);
|
|
}
|
|
|
|
void
|
|
shpcic_mem_write_1(void *v, bus_space_handle_t bsh,
|
|
bus_size_t offset, uint8_t value)
|
|
{
|
|
|
|
__shpcic_mem_write_1(bsh, offset, value);
|
|
}
|
|
|
|
void
|
|
shpcic_mem_write_2(void *v, bus_space_handle_t bsh,
|
|
bus_size_t offset, uint16_t value)
|
|
{
|
|
|
|
__shpcic_mem_write_2(bsh, offset, value);
|
|
}
|
|
|
|
void
|
|
shpcic_mem_write_4(void *v, bus_space_handle_t bsh,
|
|
bus_size_t offset, uint32_t value)
|
|
{
|
|
|
|
__shpcic_mem_write_4(bsh, offset, value);
|
|
}
|
|
|
|
/*
|
|
* write multi
|
|
*/
|
|
void
|
|
shpcic_io_write_multi_1(void *v, bus_space_handle_t bsh,
|
|
bus_size_t offset, const uint8_t *addr, bus_size_t count)
|
|
{
|
|
|
|
while (count--) {
|
|
__shpcic_io_write_1(bsh, offset, *addr++);
|
|
}
|
|
}
|
|
|
|
void
|
|
shpcic_io_write_multi_2(void *v, bus_space_handle_t bsh,
|
|
bus_size_t offset, const uint16_t *addr, bus_size_t count)
|
|
{
|
|
|
|
while (count--) {
|
|
__shpcic_io_write_2(bsh, offset, *addr++);
|
|
}
|
|
}
|
|
|
|
void
|
|
shpcic_io_write_multi_4(void *v, bus_space_handle_t bsh,
|
|
bus_size_t offset, const uint32_t *addr, bus_size_t count)
|
|
{
|
|
|
|
while (count--) {
|
|
__shpcic_io_write_4(bsh, offset, *addr++);
|
|
}
|
|
}
|
|
|
|
void
|
|
shpcic_mem_write_multi_1(void *v, bus_space_handle_t bsh,
|
|
bus_size_t offset, const uint8_t *addr, bus_size_t count)
|
|
{
|
|
|
|
while (count--) {
|
|
__shpcic_mem_write_1(bsh, offset, *addr++);
|
|
}
|
|
}
|
|
|
|
void
|
|
shpcic_mem_write_multi_2(void *v, bus_space_handle_t bsh,
|
|
bus_size_t offset, const uint16_t *addr, bus_size_t count)
|
|
{
|
|
|
|
while (count--) {
|
|
__shpcic_mem_write_2(bsh, offset, *addr++);
|
|
}
|
|
}
|
|
|
|
void
|
|
shpcic_mem_write_multi_4(void *v, bus_space_handle_t bsh,
|
|
bus_size_t offset, const uint32_t *addr, bus_size_t count)
|
|
{
|
|
|
|
while (count--) {
|
|
__shpcic_mem_write_4(bsh, offset, *addr++);
|
|
}
|
|
}
|
|
|
|
/*
|
|
* write region
|
|
*/
|
|
void
|
|
shpcic_io_write_region_1(void *v, bus_space_handle_t bsh,
|
|
bus_size_t offset, const uint8_t *addr, bus_size_t count)
|
|
{
|
|
|
|
while (count--) {
|
|
__shpcic_io_write_1(bsh, offset, *addr++);
|
|
offset += 1;
|
|
}
|
|
}
|
|
|
|
void
|
|
shpcic_io_write_region_2(void *v, bus_space_handle_t bsh,
|
|
bus_size_t offset, const uint16_t *addr, bus_size_t count)
|
|
{
|
|
|
|
while (count--) {
|
|
__shpcic_io_write_2(bsh, offset, *addr++);
|
|
offset += 2;
|
|
}
|
|
}
|
|
|
|
void
|
|
shpcic_io_write_region_4(void *v, bus_space_handle_t bsh,
|
|
bus_size_t offset, const uint32_t *addr, bus_size_t count)
|
|
{
|
|
|
|
while (count--) {
|
|
__shpcic_io_write_4(bsh, offset, *addr++);
|
|
offset += 4;
|
|
}
|
|
}
|
|
|
|
void
|
|
shpcic_mem_write_region_1(void *v, bus_space_handle_t bsh,
|
|
bus_size_t offset, const uint8_t *addr, bus_size_t count)
|
|
{
|
|
|
|
while (count--) {
|
|
__shpcic_mem_write_1(bsh, offset, *addr++);
|
|
offset += 1;
|
|
}
|
|
}
|
|
|
|
void
|
|
shpcic_mem_write_region_2(void *v, bus_space_handle_t bsh,
|
|
bus_size_t offset, const uint16_t *addr, bus_size_t count)
|
|
{
|
|
|
|
while (count--) {
|
|
__shpcic_mem_write_2(bsh, offset, *addr++);
|
|
offset += 2;
|
|
}
|
|
}
|
|
|
|
void
|
|
shpcic_mem_write_region_4(void *v, bus_space_handle_t bsh,
|
|
bus_size_t offset, const uint32_t *addr, bus_size_t count)
|
|
{
|
|
|
|
while (count--) {
|
|
__shpcic_mem_write_4(bsh, offset, *addr++);
|
|
offset += 4;
|
|
}
|
|
}
|
|
|
|
/*
|
|
* set multi
|
|
*/
|
|
void
|
|
shpcic_io_set_multi_1(void *v, bus_space_handle_t bsh,
|
|
bus_size_t offset, uint8_t value, bus_size_t count)
|
|
{
|
|
|
|
while (count--) {
|
|
__shpcic_io_write_1(bsh, offset, value);
|
|
}
|
|
}
|
|
|
|
void
|
|
shpcic_io_set_multi_2(void *v, bus_space_handle_t bsh,
|
|
bus_size_t offset, uint16_t value, bus_size_t count)
|
|
{
|
|
|
|
while (count--) {
|
|
__shpcic_io_write_2(bsh, offset, value);
|
|
}
|
|
}
|
|
|
|
void
|
|
shpcic_io_set_multi_4(void *v, bus_space_handle_t bsh,
|
|
bus_size_t offset, uint32_t value, bus_size_t count)
|
|
{
|
|
|
|
while (count--) {
|
|
__shpcic_io_write_4(bsh, offset, value);
|
|
}
|
|
}
|
|
|
|
void
|
|
shpcic_mem_set_multi_1(void *v, bus_space_handle_t bsh,
|
|
bus_size_t offset, uint8_t value, bus_size_t count)
|
|
{
|
|
|
|
while (count--) {
|
|
__shpcic_mem_write_1(bsh, offset, value);
|
|
}
|
|
}
|
|
|
|
void
|
|
shpcic_mem_set_multi_2(void *v, bus_space_handle_t bsh,
|
|
bus_size_t offset, uint16_t value, bus_size_t count)
|
|
{
|
|
|
|
while (count--) {
|
|
__shpcic_mem_write_2(bsh, offset, value);
|
|
}
|
|
}
|
|
|
|
void
|
|
shpcic_mem_set_multi_4(void *v, bus_space_handle_t bsh,
|
|
bus_size_t offset, uint32_t value, bus_size_t count)
|
|
{
|
|
|
|
while (count--) {
|
|
__shpcic_mem_write_4(bsh, offset, value);
|
|
}
|
|
}
|
|
|
|
/*
|
|
* set region
|
|
*/
|
|
void
|
|
shpcic_io_set_region_1(void *v, bus_space_handle_t bsh,
|
|
bus_size_t offset, uint8_t value, bus_size_t count)
|
|
{
|
|
|
|
while (count--) {
|
|
__shpcic_io_write_1(bsh, offset, value);
|
|
offset += 1;
|
|
}
|
|
}
|
|
|
|
void
|
|
shpcic_io_set_region_2(void *v, bus_space_handle_t bsh,
|
|
bus_size_t offset, uint16_t value, bus_size_t count)
|
|
{
|
|
|
|
while (count--) {
|
|
__shpcic_io_write_2(bsh, offset, value);
|
|
offset += 2;
|
|
}
|
|
}
|
|
|
|
void
|
|
shpcic_io_set_region_4(void *v, bus_space_handle_t bsh,
|
|
bus_size_t offset, uint32_t value, bus_size_t count)
|
|
{
|
|
|
|
while (count--) {
|
|
__shpcic_io_write_4(bsh, offset, value);
|
|
offset += 4;
|
|
}
|
|
}
|
|
|
|
void
|
|
shpcic_mem_set_region_1(void *v, bus_space_handle_t bsh,
|
|
bus_size_t offset, uint8_t value, bus_size_t count)
|
|
{
|
|
|
|
while (count--) {
|
|
__shpcic_mem_write_1(bsh, offset, value);
|
|
offset += 1;
|
|
}
|
|
}
|
|
|
|
void
|
|
shpcic_mem_set_region_2(void *v, bus_space_handle_t bsh,
|
|
bus_size_t offset, uint16_t value, bus_size_t count)
|
|
{
|
|
|
|
while (count--) {
|
|
__shpcic_mem_write_2(bsh, offset, value);
|
|
offset += 2;
|
|
}
|
|
}
|
|
|
|
void
|
|
shpcic_mem_set_region_4(void *v, bus_space_handle_t bsh,
|
|
bus_size_t offset, uint32_t value, bus_size_t count)
|
|
{
|
|
|
|
while (count--) {
|
|
__shpcic_mem_write_4(bsh, offset, value);
|
|
offset += 4;
|
|
}
|
|
}
|
|
|
|
/*
|
|
* copy region
|
|
*/
|
|
void
|
|
shpcic_io_copy_region_1(void *v, bus_space_handle_t bsh1,
|
|
bus_size_t off1, bus_space_handle_t bsh2, bus_size_t off2, bus_size_t count)
|
|
{
|
|
u_long addr1 = bsh1 + off1;
|
|
u_long addr2 = bsh2 + off2;
|
|
uint8_t value;
|
|
|
|
if (addr1 >= addr2) { /* src after dest: copy forward */
|
|
while (count--) {
|
|
value = __shpcic_io_read_1(bsh1, off1);
|
|
__shpcic_io_write_1(bsh2, off2, value);
|
|
off1 += 1;
|
|
off2 += 1;
|
|
}
|
|
} else { /* dest after src: copy backwards */
|
|
off1 += (count - 1) * 1;
|
|
off2 += (count - 1) * 1;
|
|
while (count--) {
|
|
value = __shpcic_io_read_1(bsh1, off1);
|
|
__shpcic_io_write_1(bsh2, off2, value);
|
|
off1 -= 1;
|
|
off2 -= 1;
|
|
}
|
|
}
|
|
}
|
|
|
|
void
|
|
shpcic_io_copy_region_2(void *v, bus_space_handle_t bsh1,
|
|
bus_size_t off1, bus_space_handle_t bsh2, bus_size_t off2, bus_size_t count)
|
|
{
|
|
u_long addr1 = bsh1 + off1;
|
|
u_long addr2 = bsh2 + off2;
|
|
uint16_t value;
|
|
|
|
if (addr1 >= addr2) { /* src after dest: copy forward */
|
|
while (count--) {
|
|
value = __shpcic_io_read_2(bsh1, off1);
|
|
__shpcic_io_write_2(bsh2, off2, value);
|
|
off1 += 2;
|
|
off2 += 2;
|
|
}
|
|
} else { /* dest after src: copy backwards */
|
|
off1 += (count - 1) * 2;
|
|
off2 += (count - 1) * 2;
|
|
while (count--) {
|
|
value = __shpcic_io_read_2(bsh1, off1);
|
|
__shpcic_io_write_2(bsh2, off2, value);
|
|
off1 -= 2;
|
|
off2 -= 2;
|
|
}
|
|
}
|
|
}
|
|
|
|
void
|
|
shpcic_io_copy_region_4(void *v, bus_space_handle_t bsh1,
|
|
bus_size_t off1, bus_space_handle_t bsh2, bus_size_t off2, bus_size_t count)
|
|
{
|
|
u_long addr1 = bsh1 + off1;
|
|
u_long addr2 = bsh2 + off2;
|
|
uint32_t value;
|
|
|
|
if (addr1 >= addr2) { /* src after dest: copy forward */
|
|
while (count--) {
|
|
value = __shpcic_io_read_4(bsh1, off1);
|
|
__shpcic_io_write_4(bsh2, off2, value);
|
|
off1 += 4;
|
|
off2 += 4;
|
|
}
|
|
} else { /* dest after src: copy backwards */
|
|
off1 += (count - 1) * 4;
|
|
off2 += (count - 1) * 4;
|
|
while (count--) {
|
|
value = __shpcic_io_read_4(bsh1, off1);
|
|
__shpcic_io_write_4(bsh2, off2, value);
|
|
off1 -= 4;
|
|
off2 -= 4;
|
|
}
|
|
}
|
|
}
|
|
|
|
void
|
|
shpcic_mem_copy_region_1(void *v, bus_space_handle_t bsh1,
|
|
bus_size_t off1, bus_space_handle_t bsh2, bus_size_t off2, bus_size_t count)
|
|
{
|
|
u_long addr1 = bsh1 + off1;
|
|
u_long addr2 = bsh2 + off2;
|
|
uint8_t value;
|
|
|
|
if (addr1 >= addr2) { /* src after dest: copy forward */
|
|
while (count--) {
|
|
value = __shpcic_mem_read_1(bsh1, off1);
|
|
__shpcic_mem_write_1(bsh2, off2, value);
|
|
off1 += 1;
|
|
off2 += 1;
|
|
}
|
|
} else { /* dest after src: copy backwards */
|
|
off1 += (count - 1) * 1;
|
|
off2 += (count - 1) * 1;
|
|
while (count--) {
|
|
value = __shpcic_mem_read_1(bsh1, off1);
|
|
__shpcic_mem_write_1(bsh2, off2, value);
|
|
off1 -= 1;
|
|
off2 -= 1;
|
|
}
|
|
}
|
|
}
|
|
|
|
void
|
|
shpcic_mem_copy_region_2(void *v, bus_space_handle_t bsh1,
|
|
bus_size_t off1, bus_space_handle_t bsh2, bus_size_t off2, bus_size_t count)
|
|
{
|
|
u_long addr1 = bsh1 + off1;
|
|
u_long addr2 = bsh2 + off2;
|
|
uint16_t value;
|
|
|
|
if (addr1 >= addr2) { /* src after dest: copy forward */
|
|
while (count--) {
|
|
value = __shpcic_mem_read_2(bsh1, off1);
|
|
__shpcic_mem_write_2(bsh2, off2, value);
|
|
off1 += 2;
|
|
off2 += 2;
|
|
}
|
|
} else { /* dest after src: copy backwards */
|
|
off1 += (count - 1) * 2;
|
|
off2 += (count - 1) * 2;
|
|
while (count--) {
|
|
value = __shpcic_mem_read_2(bsh1, off1);
|
|
__shpcic_mem_write_2(bsh2, off2, value);
|
|
off1 -= 2;
|
|
off2 -= 2;
|
|
}
|
|
}
|
|
}
|
|
|
|
void
|
|
shpcic_mem_copy_region_4(void *v, bus_space_handle_t bsh1,
|
|
bus_size_t off1, bus_space_handle_t bsh2, bus_size_t off2, bus_size_t count)
|
|
{
|
|
u_long addr1 = bsh1 + off1;
|
|
u_long addr2 = bsh2 + off2;
|
|
uint32_t value;
|
|
|
|
if (addr1 >= addr2) { /* src after dest: copy forward */
|
|
while (count--) {
|
|
value = __shpcic_mem_read_4(bsh1, off1);
|
|
__shpcic_mem_write_4(bsh2, off2, value);
|
|
off1 += 4;
|
|
off2 += 4;
|
|
}
|
|
} else { /* dest after src: copy backwards */
|
|
off1 += (count - 1) * 4;
|
|
off2 += (count - 1) * 4;
|
|
while (count--) {
|
|
value = __shpcic_mem_read_4(bsh1, off1);
|
|
__shpcic_mem_write_4(bsh2, off2, value);
|
|
off1 -= 4;
|
|
off2 -= 4;
|
|
}
|
|
}
|
|
}
|