34e65502e7
- read status before character, so the status won't be lost (Thomas Gerner) - accumulate as much interrupts as possible in zshard()
1214 lines
29 KiB
C
1214 lines
29 KiB
C
/* $NetBSD: zs.c,v 1.8 1995/08/20 13:28:10 leo Exp $ */
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/*
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* Copyright (c) 1995 L. Weppelman (Atari modifications)
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* Copyright (c) 1992, 1993
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* The Regents of the University of California. All rights reserved.
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*
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* This software was developed by the Computer Systems Engineering group
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* at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
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* contributed to Berkeley.
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*
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*
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* All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the University of
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* California, Lawrence Berkeley Laboratory.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the University of
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* California, Berkeley and its contributors.
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* 4. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* @(#)zs.c 8.1 (Berkeley) 7/19/93
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*/
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/*
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* Zilog Z8530 (ZSCC) driver.
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*
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* Runs two tty ports (modem2 and serial2) on zs0.
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*
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* This driver knows far too much about chip to usage mappings.
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*/
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#include <sys/param.h>
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#include <sys/proc.h>
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#include <sys/device.h>
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#include <sys/conf.h>
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#include <sys/file.h>
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#include <sys/ioctl.h>
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#include <sys/tty.h>
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#include <sys/time.h>
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#include <sys/kernel.h>
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#include <sys/syslog.h>
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#include <machine/cpu.h>
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#include <machine/iomap.h>
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#include <machine/scu.h>
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#include <machine/mfp.h>
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#include <dev/ic/z8530reg.h>
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#include <atari/dev/zsvar.h>
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#include "zs.h"
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#if NZS > 1
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#error "This driver supports only 1 85C30!"
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#endif
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#if NZS > 0
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#define PCLK (8000000) /* PCLK pin input clock rate */
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#define splzs spl5
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/*
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* Software state per found chip.
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*/
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struct zs_softc {
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struct device zi_dev; /* base device */
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volatile struct zsdevice *zi_zs; /* chip registers */
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struct zs_chanstate zi_cs[2]; /* chan A and B software state */
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};
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static u_char cb_scheduled = 0; /* Already asked for callback? */
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/*
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* Define the registers for a closed port
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*/
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static u_char zs_init_regs[16] = {
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/* 0 */ 0,
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/* 1 */ 0,
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/* 2 */ 0x60,
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/* 3 */ 0,
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/* 4 */ 0,
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/* 5 */ 0,
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/* 6 */ 0,
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/* 7 */ 0,
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/* 8 */ 0,
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/* 9 */ ZSWR9_VECTOR_INCL_STAT,
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/* 10 */ ZSWR10_NRZ,
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/* 11 */ ZSWR11_TXCLK_BAUD | ZSWR11_RXCLK_BAUD,
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/* 12 */ 0,
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/* 13 */ 0,
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/* 14 */ ZSWR14_BAUD_FROM_PCLK | ZSWR14_BAUD_ENA,
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/* 15 */ 0
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};
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/*
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* Define the machine dependant clock frequencies
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* If BRgen feeds sender/receiver we always use a
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* divisor 16, therefor the division by 16 can as
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* well be done here.
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*/
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static u_long zs_freqs_tt[] = {
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/*
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* Atari TT, RTxCB is generated by TT-MFP timer C,
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* which is set to 307.2KHz during initialisation
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* and never changed afterwards.
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*/
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PCLK/16, /* BRgen, PCLK, divisor 16 */
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229500, /* BRgen, RTxCA, divisor 16 */
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3672000, /* RTxCA, from PCLK4 */
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0, /* TRxCA, external */
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PCLK/16, /* BRgen, PCLK, divisor 16 */
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19200, /* BRgen, RTxCB, divisor 16 */
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307200, /* RTxCB, from TT-MFP TCO */
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2457600 /* TRxCB, from BCLK */
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};
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static u_long zs_freqs_falcon[] = {
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/*
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* Atari Falcon, XXX no specs available, this might be wrong
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*/
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PCLK/16, /* BRgen, PCLK, divisor 16 */
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229500, /* BRgen, RTxCA, divisor 16 */
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3672000, /* RTxCA, ??? */
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0, /* TRxCA, external */
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PCLK/16, /* BRgen, PCLK, divisor 16 */
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229500, /* BRgen, RTxCB, divisor 16 */
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3672000, /* RTxCB, ??? */
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2457600 /* TRxCB, ??? */
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};
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static u_long zs_freqs_generic[] = {
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/*
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* other machines, assume only PCLK is available
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*/
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PCLK/16, /* BRgen, PCLK, divisor 16 */
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0, /* BRgen, RTxCA, divisor 16 */
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0, /* RTxCA, unknown */
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0, /* TRxCA, unknown */
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PCLK/16, /* BRgen, PCLK, divisor 16 */
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0, /* BRgen, RTxCB, divisor 16 */
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0, /* RTxCB, unknown */
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0 /* TRxCB, unknown */
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};
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static u_long *zs_frequencies;
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/* Definition of the driver for autoconfig. */
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static int zsmatch __P((struct device *, struct cfdata *, void *));
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static void zsattach __P((struct device *, struct device *, void *));
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struct cfdriver zscd = {
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NULL, "zs", (cfmatch_t)zsmatch, zsattach, DV_TTY,
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sizeof(struct zs_softc), NULL, 0 };
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/* Interrupt handlers. */
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int zshard __P((long));
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static int zssoft __P((long));
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static int zsrint __P((struct zs_chanstate *, volatile struct zschan *));
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static int zsxint __P((struct zs_chanstate *, volatile struct zschan *));
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static int zssint __P((struct zs_chanstate *, volatile struct zschan *));
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static struct zs_chanstate *zslist;
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/* Routines called from other code. */
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static void zsstart __P((struct tty *));
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void zsstop __P((struct tty *, int));
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static int zsparam __P((struct tty *, struct termios *));
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static int zsbaudrate __P((int, int, int *, int *, int *, int *));
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/* Routines purely local to this driver. */
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static void zs_reset __P((volatile struct zschan *, int, int));
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static int zs_modem __P((struct zs_chanstate *, int, int));
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static void zs_loadchannelregs __P((volatile struct zschan *, u_char *));
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static int zsshortcuts; /* number of "shortcut" software interrupts */
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static int
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zsmatch(pdp, cfp, auxp)
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struct device *pdp;
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struct cfdata *cfp;
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void *auxp;
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{
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if(strcmp("zs", auxp) || cfp->cf_unit != 0)
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return(0);
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return(1);
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}
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/*
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* Attach a found zs.
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*/
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static void
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zsattach(parent, dev, aux)
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struct device *parent;
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struct device *dev;
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void *aux;
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{
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register struct zs_softc *zi;
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register struct zs_chanstate *cs;
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register volatile struct zsdevice *addr;
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register struct tty *tp;
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char tmp;
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addr = (struct zsdevice *)AD_SCC;
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zi = (struct zs_softc *)dev;
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zi->zi_zs = addr;
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cs = zi->zi_cs;
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/*
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* Get the command register into a known state.
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*/
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tmp = addr->zs_chan[ZS_CHAN_A].zc_csr;
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tmp = addr->zs_chan[ZS_CHAN_A].zc_csr;
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tmp = addr->zs_chan[ZS_CHAN_B].zc_csr;
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tmp = addr->zs_chan[ZS_CHAN_B].zc_csr;
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/*
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* Do a hardware reset.
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*/
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ZS_WRITE(&addr->zs_chan[ZS_CHAN_A], 9, ZSWR9_HARD_RESET);
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delay(50000); /*enough ? */
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ZS_WRITE(&addr->zs_chan[ZS_CHAN_A], 9, 0);
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/*
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* Initialize both channels
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*/
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zs_loadchannelregs(&addr->zs_chan[ZS_CHAN_A], zs_init_regs);
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zs_loadchannelregs(&addr->zs_chan[ZS_CHAN_B], zs_init_regs);
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if(machineid & ATARI_TT) {
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/*
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* ininitialise TT-MFP timer C: 307200Hz
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* timer C and D share one control register:
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* bits 0-2 control timer D
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* bits 4-6 control timer C
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*/
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int cr = MFP2->mf_tcdcr & 7;
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MFP2->mf_tcdcr = cr; /* stop timer C */
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MFP2->mf_tcdr = 1; /* counter 1 */
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cr |= T_Q004 << 4; /* divisor 4 */
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MFP2->mf_tcdcr = cr; /* start timer C */
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/*
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* enable scc related interrupts
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*/
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SCU->sys_mask |= SCU_SCC;
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zs_frequencies = zs_freqs_tt;
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} else if (machineid & ATARI_FALCON) {
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zs_frequencies = zs_freqs_falcon;
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} else {
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zs_frequencies = zs_freqs_generic;
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}
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/* link into interrupt list with order (A,B) (B=A+1) */
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cs[0].cs_next = &cs[1];
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cs[1].cs_next = zslist;
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zslist = cs;
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cs->cs_unit = 0;
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cs->cs_zc = &addr->zs_chan[ZS_CHAN_A];
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cs++;
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cs->cs_unit = 1;
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cs->cs_zc = &addr->zs_chan[ZS_CHAN_B];
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printf(": serial2 on channel a and modem2 on channel b\n");
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}
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/*
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* Open a zs serial port.
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*/
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int
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zsopen(dev, flags, mode, p)
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dev_t dev;
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int flags;
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int mode;
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struct proc *p;
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{
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register struct tty *tp;
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register struct zs_chanstate *cs;
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struct zs_softc *zi;
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int unit = ZS_UNIT(dev);
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int zs = unit >> 1;
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int error, s;
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if(zs >= zscd.cd_ndevs || (zi = zscd.cd_devs[zs]) == NULL)
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return (ENXIO);
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cs = &zi->zi_cs[unit & 1];
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tp = cs->cs_ttyp;
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if(tp == NULL) {
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cs->cs_ttyp = tp = ttymalloc();
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tp->t_dev = dev;
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tp->t_oproc = zsstart;
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tp->t_param = zsparam;
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}
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s = spltty();
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if((tp->t_state & TS_ISOPEN) == 0) {
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ttychars(tp);
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if(tp->t_ispeed == 0) {
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tp->t_iflag = TTYDEF_IFLAG;
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tp->t_oflag = TTYDEF_OFLAG;
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tp->t_cflag = TTYDEF_CFLAG;
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tp->t_lflag = TTYDEF_LFLAG;
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tp->t_ispeed = tp->t_ospeed = TTYDEF_SPEED;
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}
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(void)zsparam(tp, &tp->t_termios);
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ttsetwater(tp);
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}
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else if(tp->t_state & TS_XCLUDE && p->p_ucred->cr_uid != 0) {
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splx(s);
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return (EBUSY);
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}
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error = 0;
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for(;;) {
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/* loop, turning on the device, until carrier present */
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zs_modem(cs, ZSWR5_RTS|ZSWR5_DTR, DMSET);
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/* May never get a status intr. if DCD already on. -gwr */
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if(cs->cs_zc->zc_csr & ZSRR0_DCD)
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tp->t_state |= TS_CARR_ON;
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if(cs->cs_softcar)
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tp->t_state |= TS_CARR_ON;
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if(flags & O_NONBLOCK || tp->t_cflag & CLOCAL ||
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tp->t_state & TS_CARR_ON)
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break;
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tp->t_state |= TS_WOPEN;
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if(error = ttysleep(tp, (caddr_t)&tp->t_rawq, TTIPRI | PCATCH,
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ttopen, 0)) {
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if(!(tp->t_state & TS_ISOPEN)) {
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zs_modem(cs, 0, DMSET);
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tp->t_state &= ~TS_WOPEN;
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ttwakeup(tp);
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}
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splx(s);
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return error;
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}
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}
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splx(s);
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if(error == 0)
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error = linesw[tp->t_line].l_open(dev, tp);
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if(error)
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zs_modem(cs, 0, DMSET);
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return(error);
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}
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/*
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* Close a zs serial port.
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*/
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int
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zsclose(dev, flags, mode, p)
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dev_t dev;
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int flags;
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int mode;
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struct proc *p;
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{
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register struct zs_chanstate *cs;
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register struct tty *tp;
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struct zs_softc *zi;
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int unit = ZS_UNIT(dev);
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int s;
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zi = zscd.cd_devs[unit >> 1];
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cs = &zi->zi_cs[unit & 1];
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tp = cs->cs_ttyp;
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linesw[tp->t_line].l_close(tp, flags);
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if(tp->t_cflag & HUPCL || tp->t_state & TS_WOPEN ||
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(tp->t_state & TS_ISOPEN) == 0) {
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zs_modem(cs, 0, DMSET);
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/* hold low for 1 second */
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(void)tsleep((caddr_t)cs, TTIPRI, ttclos, hz);
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}
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if(cs->cs_creg[5] & ZSWR5_BREAK) {
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s = splzs();
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cs->cs_preg[5] &= ~ZSWR5_BREAK;
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cs->cs_creg[5] &= ~ZSWR5_BREAK;
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ZS_WRITE(cs->cs_zc, 5, cs->cs_creg[5]);
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splx(s);
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}
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ttyclose(tp);
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/*
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* Drop all lines and cancel interrupts
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*/
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zs_loadchannelregs(&zi->zi_zs->zs_chan[unit & 1], zs_init_regs);
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return (0);
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}
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/*
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* Read/write zs serial port.
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*/
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int
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zsread(dev, uio, flags)
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dev_t dev;
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struct uio *uio;
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int flags;
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{
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register struct zs_chanstate *cs;
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register struct zs_softc *zi;
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register struct tty *tp;
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int unit;
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unit = ZS_UNIT(dev);
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zi = zscd.cd_devs[unit >> 1];
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cs = &zi->zi_cs[unit & 1];
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tp = cs->cs_ttyp;
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return(linesw[tp->t_line].l_read(tp, uio, flags));
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}
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int
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zswrite(dev, uio, flags)
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dev_t dev;
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struct uio *uio;
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int flags;
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{
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register struct zs_chanstate *cs;
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register struct zs_softc *zi;
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register struct tty *tp;
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int unit;
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unit = ZS_UNIT(dev);
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zi = zscd.cd_devs[unit >> 1];
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cs = &zi->zi_cs[unit & 1];
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tp = cs->cs_ttyp;
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return(linesw[tp->t_line].l_write(tp, uio, flags));
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}
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struct tty *
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zstty(dev)
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dev_t dev;
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{
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register struct zs_chanstate *cs;
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register struct zs_softc *zi;
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int unit;
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unit = ZS_UNIT(dev);
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zi = zscd.cd_devs[unit >> 1];
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cs = &zi->zi_cs[unit & 1];
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return(cs->cs_ttyp);
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}
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/*
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* ZS hardware interrupt. Scan all ZS channels. NB: we know here that
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* channels are kept in (A,B) pairs.
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*
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* Do just a little, then get out; set a software interrupt if more
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* work is needed.
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*
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* We deliberately ignore the vectoring Zilog gives us, and match up
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* only the number of `reset interrupt under service' operations, not
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* the order.
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*/
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int
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zshard(sr)
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long sr;
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{
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register struct zs_chanstate *a;
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#define b (a + 1)
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register volatile struct zschan *zc;
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register int rr3, intflags = 0, v, i;
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do {
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intflags &= ~4;
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for(a = zslist; a != NULL; a = b->cs_next) {
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rr3 = ZS_READ(a->cs_zc, 3);
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if(rr3 & (ZSRR3_IP_A_RX|ZSRR3_IP_A_TX|ZSRR3_IP_A_STAT)) {
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intflags |= 4|2;
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zc = a->cs_zc;
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i = a->cs_rbput;
|
|
if(rr3 & ZSRR3_IP_A_RX && (v = zsrint(a, zc)) != 0) {
|
|
a->cs_rbuf[i++ & ZLRB_RING_MASK] = v;
|
|
intflags |= 1;
|
|
}
|
|
if(rr3 & ZSRR3_IP_A_TX && (v = zsxint(a, zc)) != 0) {
|
|
a->cs_rbuf[i++ & ZLRB_RING_MASK] = v;
|
|
intflags |= 1;
|
|
}
|
|
if(rr3 & ZSRR3_IP_A_STAT && (v = zssint(a, zc)) != 0) {
|
|
a->cs_rbuf[i++ & ZLRB_RING_MASK] = v;
|
|
intflags |= 1;
|
|
}
|
|
a->cs_rbput = i;
|
|
}
|
|
if(rr3 & (ZSRR3_IP_B_RX|ZSRR3_IP_B_TX|ZSRR3_IP_B_STAT)) {
|
|
intflags |= 4|2;
|
|
zc = b->cs_zc;
|
|
i = b->cs_rbput;
|
|
if(rr3 & ZSRR3_IP_B_RX && (v = zsrint(b, zc)) != 0) {
|
|
b->cs_rbuf[i++ & ZLRB_RING_MASK] = v;
|
|
intflags |= 1;
|
|
}
|
|
if(rr3 & ZSRR3_IP_B_TX && (v = zsxint(b, zc)) != 0) {
|
|
b->cs_rbuf[i++ & ZLRB_RING_MASK] = v;
|
|
intflags |= 1;
|
|
}
|
|
if(rr3 & ZSRR3_IP_B_STAT && (v = zssint(b, zc)) != 0) {
|
|
b->cs_rbuf[i++ & ZLRB_RING_MASK] = v;
|
|
intflags |= 1;
|
|
}
|
|
b->cs_rbput = i;
|
|
}
|
|
}
|
|
} while(intflags & 4);
|
|
#undef b
|
|
|
|
if(intflags & 1) {
|
|
if(BASEPRI(sr)) {
|
|
spl1();
|
|
zsshortcuts++;
|
|
return(zssoft(sr));
|
|
}
|
|
else if(!cb_scheduled) {
|
|
cb_scheduled++;
|
|
add_sicallback(zssoft, 0, 0);
|
|
}
|
|
}
|
|
return(intflags & 2);
|
|
}
|
|
|
|
static int
|
|
zsrint(cs, zc)
|
|
register struct zs_chanstate *cs;
|
|
register volatile struct zschan *zc;
|
|
{
|
|
register int c;
|
|
|
|
/*
|
|
* First read the status, because read of the received char
|
|
* destroy the status of this char.
|
|
*/
|
|
c = ZS_READ(zc, 1);
|
|
c |= (zc->zc_data << 8);
|
|
|
|
/* clear receive error & interrupt condition */
|
|
zc->zc_csr = ZSWR0_RESET_ERRORS;
|
|
zc->zc_csr = ZSWR0_CLR_INTR;
|
|
|
|
return(ZRING_MAKE(ZRING_RINT, c));
|
|
}
|
|
|
|
static int
|
|
zsxint(cs, zc)
|
|
register struct zs_chanstate *cs;
|
|
register volatile struct zschan *zc;
|
|
{
|
|
register int i = cs->cs_tbc;
|
|
|
|
if(i == 0) {
|
|
zc->zc_csr = ZSWR0_RESET_TXINT;
|
|
zc->zc_csr = ZSWR0_CLR_INTR;
|
|
return(ZRING_MAKE(ZRING_XINT, 0));
|
|
}
|
|
cs->cs_tbc = i - 1;
|
|
zc->zc_data = *cs->cs_tba++;
|
|
zc->zc_csr = ZSWR0_CLR_INTR;
|
|
return (0);
|
|
}
|
|
|
|
static int
|
|
zssint(cs, zc)
|
|
register struct zs_chanstate *cs;
|
|
register volatile struct zschan *zc;
|
|
{
|
|
register int rr0;
|
|
|
|
rr0 = zc->zc_csr;
|
|
zc->zc_csr = ZSWR0_RESET_STATUS;
|
|
zc->zc_csr = ZSWR0_CLR_INTR;
|
|
/*
|
|
* The chip's hardware flow control is, as noted in zsreg.h,
|
|
* busted---if the DCD line goes low the chip shuts off the
|
|
* receiver (!). If we want hardware CTS flow control but do
|
|
* not have it, and carrier is now on, turn HFC on; if we have
|
|
* HFC now but carrier has gone low, turn it off.
|
|
*/
|
|
if(rr0 & ZSRR0_DCD) {
|
|
if(cs->cs_ttyp->t_cflag & CCTS_OFLOW &&
|
|
(cs->cs_creg[3] & ZSWR3_HFC) == 0) {
|
|
cs->cs_creg[3] |= ZSWR3_HFC;
|
|
ZS_WRITE(zc, 3, cs->cs_creg[3]);
|
|
}
|
|
}
|
|
else {
|
|
if (cs->cs_creg[3] & ZSWR3_HFC) {
|
|
cs->cs_creg[3] &= ~ZSWR3_HFC;
|
|
ZS_WRITE(zc, 3, cs->cs_creg[3]);
|
|
}
|
|
}
|
|
return(ZRING_MAKE(ZRING_SINT, rr0));
|
|
}
|
|
|
|
/*
|
|
* Print out a ring or fifo overrun error message.
|
|
*/
|
|
static void
|
|
zsoverrun(unit, ptime, what)
|
|
int unit;
|
|
long *ptime;
|
|
char *what;
|
|
{
|
|
|
|
if(*ptime != time.tv_sec) {
|
|
*ptime = time.tv_sec;
|
|
log(LOG_WARNING, "zs%d%c: %s overrun\n", unit >> 1,
|
|
(unit & 1) + 'a', what);
|
|
}
|
|
}
|
|
|
|
/*
|
|
* ZS software interrupt. Scan all channels for deferred interrupts.
|
|
*/
|
|
int
|
|
zssoft(sr)
|
|
long sr;
|
|
{
|
|
register struct zs_chanstate *cs;
|
|
register volatile struct zschan *zc;
|
|
register struct linesw *line;
|
|
register struct tty *tp;
|
|
register int get, n, c, cc, unit, s;
|
|
int retval = 0;
|
|
|
|
cb_scheduled = 0;
|
|
s = spltty();
|
|
for(cs = zslist; cs != NULL; cs = cs->cs_next) {
|
|
get = cs->cs_rbget;
|
|
again:
|
|
n = cs->cs_rbput; /* atomic */
|
|
if(get == n) /* nothing more on this line */
|
|
continue;
|
|
retval = 1;
|
|
unit = cs->cs_unit; /* set up to handle interrupts */
|
|
zc = cs->cs_zc;
|
|
tp = cs->cs_ttyp;
|
|
line = &linesw[tp->t_line];
|
|
/*
|
|
* Compute the number of interrupts in the receive ring.
|
|
* If the count is overlarge, we lost some events, and
|
|
* must advance to the first valid one. It may get
|
|
* overwritten if more data are arriving, but this is
|
|
* too expensive to check and gains nothing (we already
|
|
* lost out; all we can do at this point is trade one
|
|
* kind of loss for another).
|
|
*/
|
|
n -= get;
|
|
if(n > ZLRB_RING_SIZE) {
|
|
zsoverrun(unit, &cs->cs_rotime, "ring");
|
|
get += n - ZLRB_RING_SIZE;
|
|
n = ZLRB_RING_SIZE;
|
|
}
|
|
while(--n >= 0) {
|
|
/* race to keep ahead of incoming interrupts */
|
|
c = cs->cs_rbuf[get++ & ZLRB_RING_MASK];
|
|
switch (ZRING_TYPE(c)) {
|
|
|
|
case ZRING_RINT:
|
|
c = ZRING_VALUE(c);
|
|
if(c & ZSRR1_DO)
|
|
zsoverrun(unit, &cs->cs_fotime, "fifo");
|
|
cc = c >> 8;
|
|
if(c & ZSRR1_FE)
|
|
cc |= TTY_FE;
|
|
if(c & ZSRR1_PE)
|
|
cc |= TTY_PE;
|
|
line->l_rint(cc, tp);
|
|
break;
|
|
|
|
case ZRING_XINT:
|
|
/*
|
|
* Transmit done: change registers and resume,
|
|
* or clear BUSY.
|
|
*/
|
|
if(cs->cs_heldchange) {
|
|
int sps;
|
|
|
|
sps = splzs();
|
|
c = zc->zc_csr;
|
|
if((c & ZSRR0_DCD) == 0)
|
|
cs->cs_preg[3] &= ~ZSWR3_HFC;
|
|
bcopy((caddr_t)cs->cs_preg,
|
|
(caddr_t)cs->cs_creg, 16);
|
|
zs_loadchannelregs(zc, cs->cs_creg);
|
|
splx(sps);
|
|
cs->cs_heldchange = 0;
|
|
if(cs->cs_heldtbc
|
|
&& (tp->t_state & TS_TTSTOP) == 0) {
|
|
cs->cs_tbc = cs->cs_heldtbc - 1;
|
|
zc->zc_data = *cs->cs_tba++;
|
|
goto again;
|
|
}
|
|
}
|
|
tp->t_state &= ~TS_BUSY;
|
|
if(tp->t_state & TS_FLUSH)
|
|
tp->t_state &= ~TS_FLUSH;
|
|
else ndflush(&tp->t_outq,cs->cs_tba
|
|
- (caddr_t)tp->t_outq.c_cf);
|
|
line->l_start(tp);
|
|
break;
|
|
|
|
case ZRING_SINT:
|
|
/*
|
|
* Status line change. HFC bit is run in
|
|
* hardware interrupt, to avoid locking
|
|
* at splzs here.
|
|
*/
|
|
c = ZRING_VALUE(c);
|
|
if((c ^ cs->cs_rr0) & ZSRR0_DCD) {
|
|
cc = (c & ZSRR0_DCD) != 0;
|
|
if(line->l_modem(tp, cc) == 0)
|
|
zs_modem(cs, ZSWR5_RTS|ZSWR5_DTR,
|
|
cc ? DMBIS : DMBIC);
|
|
}
|
|
cs->cs_rr0 = c;
|
|
break;
|
|
|
|
default:
|
|
log(LOG_ERR, "zs%d%c: bad ZRING_TYPE (%x)\n",
|
|
unit >> 1, (unit & 1) + 'a', c);
|
|
break;
|
|
}
|
|
}
|
|
cs->cs_rbget = get;
|
|
goto again;
|
|
}
|
|
splx(s);
|
|
return (retval);
|
|
}
|
|
|
|
int
|
|
zsioctl(dev, cmd, data, flag, p)
|
|
dev_t dev;
|
|
u_long cmd;
|
|
caddr_t data;
|
|
int flag;
|
|
struct proc *p;
|
|
{
|
|
int unit = ZS_UNIT(dev);
|
|
struct zs_softc *zi = zscd.cd_devs[unit >> 1];
|
|
register struct tty *tp = zi->zi_cs[unit & 1].cs_ttyp;
|
|
register int error, s;
|
|
register struct zs_chanstate *cs = &zi->zi_cs[unit & 1];
|
|
|
|
error = linesw[tp->t_line].l_ioctl(tp, cmd, data, flag, p);
|
|
if(error >= 0)
|
|
return(error);
|
|
error = ttioctl(tp, cmd, data, flag, p);
|
|
if(error >= 0)
|
|
return (error);
|
|
|
|
switch (cmd) {
|
|
case TIOCSBRK:
|
|
s = splzs();
|
|
cs->cs_preg[5] |= ZSWR5_BREAK;
|
|
cs->cs_creg[5] |= ZSWR5_BREAK;
|
|
ZS_WRITE(cs->cs_zc, 5, cs->cs_creg[5]);
|
|
splx(s);
|
|
break;
|
|
case TIOCCBRK:
|
|
s = splzs();
|
|
cs->cs_preg[5] &= ~ZSWR5_BREAK;
|
|
cs->cs_creg[5] &= ~ZSWR5_BREAK;
|
|
ZS_WRITE(cs->cs_zc, 5, cs->cs_creg[5]);
|
|
splx(s);
|
|
break;
|
|
case TIOCGFLAGS: {
|
|
int bits = 0;
|
|
|
|
if(cs->cs_softcar)
|
|
bits |= TIOCFLAG_SOFTCAR;
|
|
if(cs->cs_creg[15] & ZSWR15_DCD_IE)
|
|
bits |= TIOCFLAG_CLOCAL;
|
|
if(cs->cs_creg[3] & ZSWR3_HFC)
|
|
bits |= TIOCFLAG_CRTSCTS;
|
|
*(int *)data = bits;
|
|
break;
|
|
}
|
|
case TIOCSFLAGS: {
|
|
int userbits, driverbits = 0;
|
|
|
|
error = suser(p->p_ucred, &p->p_acflag);
|
|
if(error != 0)
|
|
return (EPERM);
|
|
|
|
userbits = *(int *)data;
|
|
|
|
/*
|
|
* can have `local' or `softcar', and `rtscts' or `mdmbuf'
|
|
# defaulting to software flow control.
|
|
*/
|
|
if(userbits & TIOCFLAG_SOFTCAR && userbits & TIOCFLAG_CLOCAL)
|
|
return(EINVAL);
|
|
if(userbits & TIOCFLAG_MDMBUF) /* don't support this (yet?) */
|
|
return(ENXIO);
|
|
|
|
s = splzs();
|
|
if((userbits & TIOCFLAG_SOFTCAR)) {
|
|
cs->cs_softcar = 1; /* turn on softcar */
|
|
cs->cs_preg[15] &= ~ZSWR15_DCD_IE; /* turn off dcd */
|
|
cs->cs_creg[15] &= ~ZSWR15_DCD_IE;
|
|
ZS_WRITE(cs->cs_zc, 15, cs->cs_creg[15]);
|
|
}
|
|
else if(userbits & TIOCFLAG_CLOCAL) {
|
|
cs->cs_softcar = 0; /* turn off softcar */
|
|
cs->cs_preg[15] |= ZSWR15_DCD_IE; /* turn on dcd */
|
|
cs->cs_creg[15] |= ZSWR15_DCD_IE;
|
|
ZS_WRITE(cs->cs_zc, 15, cs->cs_creg[15]);
|
|
tp->t_termios.c_cflag |= CLOCAL;
|
|
}
|
|
if(userbits & TIOCFLAG_CRTSCTS) {
|
|
cs->cs_preg[15] |= ZSWR15_CTS_IE;
|
|
cs->cs_creg[15] |= ZSWR15_CTS_IE;
|
|
ZS_WRITE(cs->cs_zc, 15, cs->cs_creg[15]);
|
|
cs->cs_preg[3] |= ZSWR3_HFC;
|
|
cs->cs_creg[3] |= ZSWR3_HFC;
|
|
ZS_WRITE(cs->cs_zc, 3, cs->cs_creg[3]);
|
|
tp->t_termios.c_cflag |= CRTSCTS;
|
|
}
|
|
else {
|
|
/* no mdmbuf, so we must want software flow control */
|
|
cs->cs_preg[15] &= ~ZSWR15_CTS_IE;
|
|
cs->cs_creg[15] &= ~ZSWR15_CTS_IE;
|
|
ZS_WRITE(cs->cs_zc, 15, cs->cs_creg[15]);
|
|
cs->cs_preg[3] &= ~ZSWR3_HFC;
|
|
cs->cs_creg[3] &= ~ZSWR3_HFC;
|
|
ZS_WRITE(cs->cs_zc, 3, cs->cs_creg[3]);
|
|
tp->t_termios.c_cflag &= ~CRTSCTS;
|
|
}
|
|
splx(s);
|
|
break;
|
|
}
|
|
case TIOCSDTR:
|
|
zs_modem(cs, ZSWR5_DTR, DMBIS);
|
|
break;
|
|
case TIOCCDTR:
|
|
zs_modem(cs, ZSWR5_DTR, DMBIC);
|
|
break;
|
|
case TIOCMGET:
|
|
zs_modem(cs, 0, DMGET);
|
|
break;
|
|
case TIOCMSET:
|
|
case TIOCMBIS:
|
|
case TIOCMBIC:
|
|
default:
|
|
return (ENOTTY);
|
|
}
|
|
return (0);
|
|
}
|
|
|
|
/*
|
|
* Start or restart transmission.
|
|
*/
|
|
static void
|
|
zsstart(tp)
|
|
register struct tty *tp;
|
|
{
|
|
register struct zs_chanstate *cs;
|
|
register int s, nch;
|
|
int unit = ZS_UNIT(tp->t_dev);
|
|
struct zs_softc *zi = zscd.cd_devs[unit >> 1];
|
|
|
|
cs = &zi->zi_cs[unit & 1];
|
|
s = spltty();
|
|
|
|
/*
|
|
* If currently active or delaying, no need to do anything.
|
|
*/
|
|
if(tp->t_state & (TS_TIMEOUT | TS_BUSY | TS_TTSTOP))
|
|
goto out;
|
|
|
|
/*
|
|
* If there are sleepers, and output has drained below low
|
|
* water mark, awaken.
|
|
*/
|
|
if(tp->t_outq.c_cc <= tp->t_lowat) {
|
|
if(tp->t_state & TS_ASLEEP) {
|
|
tp->t_state &= ~TS_ASLEEP;
|
|
wakeup((caddr_t)&tp->t_outq);
|
|
}
|
|
selwakeup(&tp->t_wsel);
|
|
}
|
|
|
|
nch = ndqb(&tp->t_outq, 0); /* XXX */
|
|
if(nch) {
|
|
register char *p = tp->t_outq.c_cf;
|
|
|
|
/* mark busy, enable tx done interrupts, & send first byte */
|
|
tp->t_state |= TS_BUSY;
|
|
(void) splzs();
|
|
cs->cs_preg[1] |= ZSWR1_TIE;
|
|
cs->cs_creg[1] |= ZSWR1_TIE;
|
|
ZS_WRITE(cs->cs_zc, 1, cs->cs_creg[1]);
|
|
cs->cs_zc->zc_data = *p;
|
|
cs->cs_tba = p + 1;
|
|
cs->cs_tbc = nch - 1;
|
|
} else {
|
|
/*
|
|
* Nothing to send, turn off transmit done interrupts.
|
|
* This is useful if something is doing polled output.
|
|
*/
|
|
(void) splzs();
|
|
cs->cs_preg[1] &= ~ZSWR1_TIE;
|
|
cs->cs_creg[1] &= ~ZSWR1_TIE;
|
|
ZS_WRITE(cs->cs_zc, 1, cs->cs_creg[1]);
|
|
}
|
|
out:
|
|
splx(s);
|
|
}
|
|
|
|
/*
|
|
* Stop output, e.g., for ^S or output flush.
|
|
*/
|
|
void
|
|
zsstop(tp, flag)
|
|
register struct tty *tp;
|
|
int flag;
|
|
{
|
|
register struct zs_chanstate *cs;
|
|
register int s, unit = ZS_UNIT(tp->t_dev);
|
|
struct zs_softc *zi = zscd.cd_devs[unit >> 1];
|
|
|
|
cs = &zi->zi_cs[unit & 1];
|
|
s = splzs();
|
|
if(tp->t_state & TS_BUSY) {
|
|
/*
|
|
* Device is transmitting; must stop it.
|
|
*/
|
|
cs->cs_tbc = 0;
|
|
if ((tp->t_state & TS_TTSTOP) == 0)
|
|
tp->t_state |= TS_FLUSH;
|
|
}
|
|
splx(s);
|
|
}
|
|
|
|
/*
|
|
* Set ZS tty parameters from termios.
|
|
*
|
|
* This routine makes use of the fact that only registers
|
|
* 1, 3, 4, 5, 9, 10, 11, 12, 13, 14, and 15 are written.
|
|
*/
|
|
static int
|
|
zsparam(tp, t)
|
|
register struct tty *tp;
|
|
register struct termios *t;
|
|
{
|
|
int unit = ZS_UNIT(tp->t_dev);
|
|
struct zs_softc *zi = zscd.cd_devs[unit >> 1];
|
|
register struct zs_chanstate *cs = &zi->zi_cs[unit & 1];
|
|
int cdiv, clkm, brgm, tcon;
|
|
register int tmp, tmp5, cflag, s;
|
|
|
|
tmp = t->c_ospeed;
|
|
tmp5 = t->c_ispeed;
|
|
if(tmp < 0 || (tmp5 && tmp5 != tmp))
|
|
return(EINVAL);
|
|
if(tmp == 0) {
|
|
/* stty 0 => drop DTR and RTS */
|
|
zs_modem(cs, 0, DMSET);
|
|
return(0);
|
|
}
|
|
tmp = zsbaudrate(unit, tmp, &cdiv, &clkm, &brgm, &tcon);
|
|
if (tmp < 0)
|
|
return(EINVAL);
|
|
tp->t_ispeed = tp->t_ospeed = tmp;
|
|
|
|
cflag = tp->t_cflag = t->c_cflag;
|
|
if (cflag & CSTOPB)
|
|
cdiv |= ZSWR4_TWOSB;
|
|
else
|
|
cdiv |= ZSWR4_ONESB;
|
|
if (!(cflag & PARODD))
|
|
cdiv |= ZSWR4_EVENP;
|
|
if (cflag & PARENB)
|
|
cdiv |= ZSWR4_PARENB;
|
|
|
|
switch(cflag & CSIZE) {
|
|
case CS5:
|
|
tmp = ZSWR3_RX_5;
|
|
tmp5 = ZSWR5_TX_5;
|
|
break;
|
|
case CS6:
|
|
tmp = ZSWR3_RX_6;
|
|
tmp5 = ZSWR5_TX_6;
|
|
break;
|
|
case CS7:
|
|
tmp = ZSWR3_RX_7;
|
|
tmp5 = ZSWR5_TX_7;
|
|
break;
|
|
case CS8:
|
|
default:
|
|
tmp = ZSWR3_RX_8;
|
|
tmp5 = ZSWR5_TX_8;
|
|
break;
|
|
}
|
|
tmp |= ZSWR3_RX_ENABLE;
|
|
tmp5 |= ZSWR5_TX_ENABLE | ZSWR5_DTR | ZSWR5_RTS;
|
|
|
|
/*
|
|
* Block interrupts so that state will not
|
|
* be altered until we are done setting it up.
|
|
*/
|
|
s = splzs();
|
|
cs->cs_preg[4] = cdiv;
|
|
cs->cs_preg[11] = clkm;
|
|
cs->cs_preg[12] = tcon;
|
|
cs->cs_preg[13] = tcon >> 8;
|
|
cs->cs_preg[14] = brgm;
|
|
cs->cs_preg[1] = ZSWR1_RIE | ZSWR1_TIE | ZSWR1_SIE;
|
|
cs->cs_preg[9] = ZSWR9_MASTER_IE | ZSWR9_VECTOR_INCL_STAT;
|
|
cs->cs_preg[10] = ZSWR10_NRZ;
|
|
cs->cs_preg[15] = ZSWR15_BREAK_IE | ZSWR15_DCD_IE;
|
|
|
|
/*
|
|
* Output hardware flow control on the chip is horrendous: if
|
|
* carrier detect drops, the receiver is disabled. Hence we
|
|
* can only do this when the carrier is on.
|
|
*/
|
|
if(cflag & CCTS_OFLOW && cs->cs_zc->zc_csr & ZSRR0_DCD)
|
|
tmp |= ZSWR3_HFC;
|
|
cs->cs_preg[3] = tmp;
|
|
cs->cs_preg[5] = tmp5;
|
|
|
|
/*
|
|
* If nothing is being transmitted, set up new current values,
|
|
* else mark them as pending.
|
|
*/
|
|
if(cs->cs_heldchange == 0) {
|
|
if (cs->cs_ttyp->t_state & TS_BUSY) {
|
|
cs->cs_heldtbc = cs->cs_tbc;
|
|
cs->cs_tbc = 0;
|
|
cs->cs_heldchange = 1;
|
|
} else {
|
|
bcopy((caddr_t)cs->cs_preg, (caddr_t)cs->cs_creg, 16);
|
|
zs_loadchannelregs(cs->cs_zc, cs->cs_creg);
|
|
}
|
|
}
|
|
splx(s);
|
|
return (0);
|
|
}
|
|
|
|
/*
|
|
* search for the best matching baudrate
|
|
*/
|
|
static int
|
|
zsbaudrate(unit, wanted, divisor, clockmode, brgenmode, timeconst)
|
|
int unit, wanted, *divisor, *clockmode, *brgenmode, *timeconst;
|
|
{
|
|
int bestdiff, bestbps, source;
|
|
|
|
unit = (unit & 1) << 2;
|
|
for (source = 0; source < 4; ++source) {
|
|
long freq = zs_frequencies[unit + source];
|
|
int diff, bps, div, clkm, brgm, tcon;
|
|
switch (source) {
|
|
case 0: /* BRgen, PCLK */
|
|
brgm = ZSWR14_BAUD_ENA|ZSWR14_BAUD_FROM_PCLK;
|
|
break;
|
|
case 1: /* BRgen, RTxC */
|
|
brgm = ZSWR14_BAUD_ENA;
|
|
break;
|
|
case 2: /* RTxC */
|
|
clkm = ZSWR11_RXCLK_RTXC|ZSWR11_TXCLK_RTXC;
|
|
break;
|
|
case 3: /* TRxC */
|
|
clkm = ZSWR11_RXCLK_TRXC|ZSWR11_TXCLK_TRXC;
|
|
break;
|
|
}
|
|
switch (source) {
|
|
case 0:
|
|
case 1:
|
|
div = ZSWR4_CLK_X16;
|
|
clkm = ZSWR11_RXCLK_BAUD|ZSWR11_TXCLK_BAUD;
|
|
tcon = BPS_TO_TCONST(freq, wanted);
|
|
if (tcon < 0)
|
|
tcon = 0;
|
|
bps = TCONST_TO_BPS(freq, tcon);
|
|
break;
|
|
case 2:
|
|
case 3:
|
|
{ int b1 = freq / 16, d1 = abs(b1 - wanted);
|
|
int b2 = freq / 32, d2 = abs(b2 - wanted);
|
|
int b3 = freq / 64, d3 = abs(b3 - wanted);
|
|
|
|
if (d1 < d2 && d1 < d3) {
|
|
div = ZSWR4_CLK_X16;
|
|
bps = b1;
|
|
} else if (d2 < d3 && d2 < d1) {
|
|
div = ZSWR4_CLK_X32;
|
|
bps = b2;
|
|
} else {
|
|
div = ZSWR4_CLK_X64;
|
|
bps = b3;
|
|
}
|
|
brgm = tcon = 0;
|
|
break;
|
|
}
|
|
}
|
|
diff = abs(bps - wanted);
|
|
if (!source || diff < bestdiff) {
|
|
*divisor = div;
|
|
*clockmode = clkm;
|
|
*brgenmode = brgm;
|
|
*timeconst = tcon;
|
|
bestbps = bps;
|
|
bestdiff = diff;
|
|
if (diff == 0)
|
|
break;
|
|
}
|
|
}
|
|
/* Allow deviations upto 5% */
|
|
if (20 * bestdiff > wanted)
|
|
return -1;
|
|
return bestbps;
|
|
}
|
|
|
|
/*
|
|
* Raise or lower modem control (DTR/RTS) signals. If a character is
|
|
* in transmission, the change is deferred.
|
|
*/
|
|
static int
|
|
zs_modem(cs, bits, how)
|
|
struct zs_chanstate *cs;
|
|
int bits, how;
|
|
{
|
|
int s, mbits;
|
|
|
|
bits &= ZSWR5_DTR | ZSWR5_RTS;
|
|
|
|
s = splzs();
|
|
mbits = cs->cs_preg[5] & (ZSWR5_DTR | ZSWR5_RTS);
|
|
|
|
switch(how) {
|
|
case DMSET:
|
|
mbits = bits;
|
|
break;
|
|
case DMBIS:
|
|
mbits |= bits;
|
|
break;
|
|
case DMBIC:
|
|
mbits &= ~bits;
|
|
break;
|
|
case DMGET:
|
|
splx(s);
|
|
return(mbits);
|
|
}
|
|
|
|
cs->cs_preg[5] = (cs->cs_preg[5] & ~(ZSWR5_DTR | ZSWR5_RTS)) | mbits;
|
|
if(cs->cs_heldchange == 0) {
|
|
if(cs->cs_ttyp->t_state & TS_BUSY) {
|
|
cs->cs_heldtbc = cs->cs_tbc;
|
|
cs->cs_tbc = 0;
|
|
cs->cs_heldchange = 1;
|
|
}
|
|
else {
|
|
ZS_WRITE(cs->cs_zc, 5, cs->cs_creg[5]);
|
|
}
|
|
}
|
|
splx(s);
|
|
return(0);
|
|
}
|
|
|
|
/*
|
|
* Write the given register set to the given zs channel in the proper order.
|
|
* The channel must not be transmitting at the time. The receiver will
|
|
* be disabled for the time it takes to write all the registers.
|
|
*/
|
|
static void
|
|
zs_loadchannelregs(zc, reg)
|
|
volatile struct zschan *zc;
|
|
u_char *reg;
|
|
{
|
|
int i;
|
|
|
|
zc->zc_csr = ZSM_RESET_ERR; /* reset error condition */
|
|
i = zc->zc_data; /* drain fifo */
|
|
i = zc->zc_data;
|
|
i = zc->zc_data;
|
|
ZS_WRITE(zc, 4, reg[4]);
|
|
ZS_WRITE(zc, 10, reg[10]);
|
|
ZS_WRITE(zc, 3, reg[3] & ~ZSWR3_RX_ENABLE);
|
|
ZS_WRITE(zc, 5, reg[5] & ~ZSWR5_TX_ENABLE);
|
|
ZS_WRITE(zc, 1, reg[1]);
|
|
ZS_WRITE(zc, 9, reg[9]);
|
|
ZS_WRITE(zc, 11, reg[11]);
|
|
ZS_WRITE(zc, 12, reg[12]);
|
|
ZS_WRITE(zc, 13, reg[13]);
|
|
ZS_WRITE(zc, 14, reg[14]);
|
|
ZS_WRITE(zc, 15, reg[15]);
|
|
ZS_WRITE(zc, 3, reg[3]);
|
|
ZS_WRITE(zc, 5, reg[5]);
|
|
}
|
|
#endif /* NZS > 1 */
|