241 lines
10 KiB
C
241 lines
10 KiB
C
/* $NetBSD: sgecreg.h,v 1.3 2003/08/07 16:31:03 agc Exp $ */
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/*
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* Copyright (c) 1988 Regents of the University of California.
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* All rights reserved.
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*
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* This code is derived from software contributed to Berkeley by
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* Digital Equipment Corp.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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*/
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#ifndef _DEV_IC_SGECREG_H_
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#define _DEV_IC_SGECREG_H_
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/* Driver for SGEC (second generation Ethernet controller) chip, type DC-541,
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found on the KA670 (and prob ably other) CPU.
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17 May 1998...Jay Maynard, jmaynard@phoenix.net
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*/
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/* SGEC CSRs */
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struct zedevice {
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u_long ze_nicsr0; /* vector address, IPL, sync mode */
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u_long ze_nicsr1; /* TX poll demand */
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u_long ze_nicsr2; /* RX poll demand */
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struct ze_rdes *ze_nicsr3; /* RX descriptor list address */
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struct ze_tdes *ze_nicsr4; /* TX descriptor list address */
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u_long ze_nicsr5; /* SGEC status */
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u_long ze_nicsr6; /* SGEC command/mode */
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u_long ze_nicsr7; /* system page table base address */
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u_long ze_nivcsr8; /* reserved virtual CSR */
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u_long ze_nivcsr9; /* watchdog timers (virtual) */
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u_long ze_nivcsr10; /* revision, missed frame count (v) */
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u_long ze_nivcsr11; /* boot message verification (low) (v) */
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u_long ze_nivcsr12; /* boot message verification (high) (v) */
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u_long ze_nivcsr13; /* boot message processor (v) */
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u_long ze_nivcsr14; /* diagnostic breakpoint (v) */
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u_long ze_nicsr15; /* monitor command */
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};
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/*
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* Register offsets.
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*/
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#define ZE_CSR0 0
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#define ZE_CSR1 4
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#define ZE_CSR2 8
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#define ZE_CSR3 12
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#define ZE_CSR4 16
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#define ZE_CSR5 20
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#define ZE_CSR6 24
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#define ZE_CSR7 28
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#define ZE_CSR8 32
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#define ZE_CSR9 36
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#define ZE_CSR10 40
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#define ZE_CSR11 44
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#define ZE_CSR12 48
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#define ZE_CSR13 52
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#define ZE_CSR14 56
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#define ZE_CSR15 60
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/* SGEC bit definitions */
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/* NICSR0: */
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#define ZE_NICSR0_IPL 0xc0000000 /* interrupt priority level: */
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#define ZE_NICSR0_IPL14 0x00000000 /* 0x14 */
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#define ZE_NICSR0_IPL15 0x40000000 /* 0x15 */
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#define ZE_NICSR0_IPL16 0x80000000 /* 0x16 */
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#define ZE_NICSR0_IPL17 0xc0000000 /* 0x17 */
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#define ZE_NICSR0_SA 0x20000000 /* sync(1)/async mode */
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#define ZE_NICSR0_MBO 0x1fff0003 /* must be set to one on write */
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#define ZE_NICSR0_IV_MASK 0x0000fffc /* bits for the interrupt vector */
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/* NICSR1: */
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#define ZE_NICSR1_TXPD 0xffffffff /* transmit polling demand */
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/* NICSR2: */
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#define ZE_NICSR2_RXPD 0xffffffff /* receive polling demand */
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/* NICSR3 and NICSR4 are pure addresses */
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/* NICSR5: */
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#define ZE_NICSR5_ID 0x80000000 /* init done */
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#define ZE_NICSR5_SF 0x40000000 /* self-test failed */
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#define ZE_NICSR5_SS 0x3c000000 /* self-test status field */
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#define ZE_NICSR5_TS 0x03000000 /* transmission state: */
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#define ZE_NICSR5_TS_STOP 0x00000000 /* stopped */
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#define ZE_NICSR5_TS_RUN 0x01000000 /* running */
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#define ZE_NICSR5_TS_SUSP 0x02000000 /* suspended */
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#define ZE_NICSR5_RS 0x00c00000 /* reception state: */
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#define ZE_NICSR5_RS_STOP 0x00000000 /* stopped */
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#define ZE_NICSR5_RS_RUN 0x00400000 /* running */
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#define ZE_NICSR5_RS_SUSP 0x00800000 /* suspended */
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#define ZE_NICSR5_OM 0x00060000 /* operating mode: */
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#define ZE_NICSR5_OM_NORM 0x00000000 /* normal */
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#define ZE_NICSR5_OM_ILBK 0x00020000 /* internal loopback */
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#define ZE_NICSR5_OM_ELBK 0x00040000 /* external loopback */
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#define ZE_NICSR5_OM_DIAG 0x00060000 /* reserved for diags */
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#define ZE_NICSR5_DN 0x00010000 /* virtual CSR access done */
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#define ZE_NICSR5_MBO 0x0038ff00 /* must be one */
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#define ZE_NICSR5_BO 0x00000080 /* boot message received */
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#define ZE_NICSR5_TW 0x00000040 /* transmit watchdog timeout */
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#define ZE_NICSR5_RW 0x00000020 /* receive watchdog timeout */
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#define ZE_NICSR5_ME 0x00000010 /* memory error */
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#define ZE_NICSR5_RU 0x00000008 /* receive buffer unavailable */
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#define ZE_NICSR5_RI 0x00000004 /* receiver interrupt */
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#define ZE_NICSR5_TI 0x00000002 /* transmitter interrupt */
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#define ZE_NICSR5_IS 0x00000001 /* interrupt summary */
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/* whew! */
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/* NICSR6: */
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#define ZE_NICSR6_RE 0x80000000 /* reset */
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#define ZE_NICSR6_IE 0x40000000 /* interrupt enable */
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#define ZE_NICSR6_MBO 0x01e7f000 /* must be one */
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#define ZE_NICSR6_BL 0x1e000000 /* burst limit mask */
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#define ZE_NICSR6_BL_8 0x10000000 /* 8 longwords */
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#define ZE_NICSR6_BL_4 0x08000000 /* 4 longwords */
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#define ZE_NICSR6_BL_2 0x04000000 /* 2 longwords */
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#define ZE_NICSR6_BL_1 0x02000000 /* 1 longword */
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#define ZE_NICSR6_BE 0x00100000 /* boot message enable */
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#define ZE_NICSR6_SE 0x00080000 /* single cycle enable */
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#define ZE_NICSR6_ST 0x00000800 /* start(1)/stop(0) transmission */
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#define ZE_NICSR6_SR 0x00000400 /* start(1)/stop(0) reception */
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#define ZE_NICSR6_OM 0x00000300 /* operating mode: */
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#define ZE_NICSR6_OM_NORM 0x00000000 /* normal */
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#define ZE_NICSR6_OM_ILBK 0x00000100 /* internal loopback */
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#define ZE_NICSR6_OM_ELBK 0x00000200 /* external loopback */
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#define ZE_NICSR6_OM_DIAG 0x00000300 /* reserved for diags */
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#define ZE_NICSR6_DC 0x00000080 /* disable data chaining */
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#define ZE_NICSR6_FC 0x00000040 /* force collision mode */
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#define ZE_NICSR6_PB 0x00000008 /* pass bad frames */
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#define ZE_NICSR6_AF 0x00000006 /* address filtering mode: */
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#define ZE_NICSR6_AF_NORM 0x00000000 /* normal filtering */
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#define ZE_NICSR6_AF_PROM 0x00000002 /* promiscuous mode */
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#define ZE_NICSR6_AF_ALLM 0x00000004 /* all multicasts */
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/* NICSR7 is an address, NICSR8 is reserved */
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/* NICSR9: */
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#define ZE_VNICSR9_RT 0xffff0000 /* receiver timeout, *1.6 us */
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#define ZE_VNICSR9_TT 0x0000ffff /* transmitter timeout */
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/* NICSR10: */
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#define ZE_VNICSR10_RN 0x001f0000 /* SGEC version */
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#define ZE_VNICSR10_MFC 0x0000ffff /* missed frame counter */
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/* if you want to know what's in NICSRs 11-15, define them yourself! */
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/* Descriptors: */
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/* Receive descriptor */
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struct ze_rdes {
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u_short ze_rdes0; /* descriptor word 0 flags */
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u_short ze_framelen; /* received frame length */
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u_char ze_rsvd1[3]; /* unused bytes */
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u_char ze_rdes1; /* descriptor word 1 flags */
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short ze_pageoffset; /* offset of buffer in page */
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short ze_bufsize; /* length of data buffer */
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u_char *ze_bufaddr; /* address of data buffer */
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};
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/* Receive descriptor bits */
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#define ZE_FRAMELEN_OW 0x8000 /* SGEC owns this descriptor */
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#define ZE_RDES0_ES 0x8000 /* an error has occurred */
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#define ZE_RDES0_LE 0x4000 /* length error */
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#define ZE_RDES0_DT 0x3000 /* data type: */
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#define ZE_RDES0_DT_NORM 0x0000 /* normal frame */
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#define ZE_RDES0_DT_ILBK 0x1000 /* internally looped back frame */
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#define ZE_RDES0_DT_ELBK 0x2000 /* externally looped back frame */
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#define ZE_RDES0_RF 0x0800 /* runt frame */
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#define ZE_RDES0_BO 0x0400 /* buffer overflow */
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#define ZE_RDES0_FS 0x0200 /* first segment */
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#define ZE_RDES0_LS 0x0100 /* last segment */
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#define ZE_RDES0_TL 0x0080 /* frame too long */
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#define ZE_RDES0_CS 0x0040 /* collision seen */
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#define ZE_RDES0_FT 0x0020 /* Ethernet frame type */
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#define ZE_RDES0_TN 0x0008 /* address translation not valid */
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#define ZE_RDES0_DB 0x0004 /* dribbling bits seen */
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#define ZE_RDES0_CE 0x0002 /* CRC error */
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#define ZE_RDES0_OF 0x0001 /* internal FIFO overflow */
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#define ZE_RDES1_CA 0x80 /* chain address */
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#define ZE_RDES1_VA 0x40 /* virtual address */
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#define ZE_RDES1_VT 0x20 /* virtual(1)/phys PTE address */
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/* Transmit descriptor */
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struct ze_tdes {
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u_short ze_tdes0; /* descriptor word 0 flags */
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u_short ze_tdr; /* TDR count of cable fault */
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u_char ze_rsvd1[2]; /* unused bytes */
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u_short ze_tdes1; /* descriptor word 1 flags */
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short ze_pageoffset; /* offset of buffer in page */
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short ze_bufsize; /* length of data buffer */
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u_char *ze_bufaddr; /* address of data buffer */
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};
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/* Receive descriptor bits */
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#define ZE_TDR_OW 0x8000 /* SGEC owns this descriptor */
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#define ZE_TDES0_ES 0x8000 /* an error has occurred */
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#define ZE_TDES0_TO 0x4000 /* transmit watchdog timeout */
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#define ZE_TDES0_LE 0x1000 /* length error */
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#define ZE_TDES0_LO 0x0800 /* loss of carrier */
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#define ZE_TDES0_NC 0x0400 /* no carrier */
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#define ZE_TDES0_LC 0x0200 /* late collision */
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#define ZE_TDES0_EC 0x0100 /* excessive collisions */
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#define ZE_TDES0_HF 0x0080 /* heartbeat fail */
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#define ZE_TDES0_CC 0x0078 /* collision count mask */
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#define ZE_TDES0_TN 0x0004 /* address translation invalid */
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#define ZE_TDES0_UF 0x0002 /* underflow */
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#define ZE_TDES0_DE 0x0001 /* transmission deferred */
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#define ZE_TDES1_CA 0x8000 /* chain address */
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#define ZE_TDES1_VA 0x4000 /* virtual address */
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#define ZE_TDES1_DT 0x3000 /* data type: */
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#define ZE_TDES1_DT_NORM 0x0000 /* normal transmit frame */
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#define ZE_TDES1_DT_SETUP 0x2000 /* setup frame */
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#define ZE_TDES1_DT_DIAG 0x3000 /* diagnostic frame */
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#define ZE_TDES1_AC 0x0800 /* CRC disable */
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#define ZE_TDES1_FS 0x0400 /* first segment */
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#define ZE_TDES1_LS 0x0200 /* last segment */
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#define ZE_TDES1_IC 0x0100 /* interrupt on completion */
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#define ZE_TDES1_VT 0x0080 /* virtual(1)/phys PTE address */
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#endif /* _DEV_IC_SGECREG_H_ */
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