1127 lines
28 KiB
C
1127 lines
28 KiB
C
/* $NetBSD: isa_machdep.c,v 1.37 1998/08/05 16:34:36 augustss Exp $ */
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#define ISA_DMA_STATS
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/*-
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* Copyright (c) 1996, 1997, 1998 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
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* NASA Ames Research Center.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the NetBSD
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* Foundation, Inc. and its contributors.
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* 4. Neither the name of The NetBSD Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*-
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* Copyright (c) 1993, 1994, 1996, 1997
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* Charles M. Hannum. All rights reserved.
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* Copyright (c) 1991 The Regents of the University of California.
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* All rights reserved.
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*
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* This code is derived from software contributed to Berkeley by
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* William Jolitz.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the University of
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* California, Berkeley and its contributors.
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* 4. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* @(#)isa.c 7.2 (Berkeley) 5/13/91
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*/
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/syslog.h>
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#include <sys/device.h>
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#include <sys/malloc.h>
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#include <sys/proc.h>
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#include <sys/mbuf.h>
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#define _I386_BUS_DMA_PRIVATE
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#include <machine/bus.h>
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#include <machine/pio.h>
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#include <machine/cpufunc.h>
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#include <dev/isa/isareg.h>
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#include <dev/isa/isavar.h>
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#include <i386/isa/isa_machdep.h>
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#include <i386/isa/icu.h>
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#include <vm/vm.h>
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/*
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* ISA can only DMA to 0-16M.
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*/
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#define ISA_DMA_BOUNCE_THRESHOLD (16 * 1024 * 1024)
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extern vm_offset_t avail_end;
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#define IDTVEC(name) __CONCAT(X,name)
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typedef void (vector) __P((void));
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extern vector *IDTVEC(intr)[];
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void isa_strayintr __P((int));
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void intr_calculatemasks __P((void));
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int fakeintr __P((void *));
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int _isa_bus_dmamap_create __P((bus_dma_tag_t, bus_size_t, int,
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bus_size_t, bus_size_t, int, bus_dmamap_t *));
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void _isa_bus_dmamap_destroy __P((bus_dma_tag_t, bus_dmamap_t));
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int _isa_bus_dmamap_load __P((bus_dma_tag_t, bus_dmamap_t, void *,
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bus_size_t, struct proc *, int));
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int _isa_bus_dmamap_load_mbuf __P((bus_dma_tag_t, bus_dmamap_t,
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struct mbuf *, int));
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int _isa_bus_dmamap_load_uio __P((bus_dma_tag_t, bus_dmamap_t,
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struct uio *, int));
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int _isa_bus_dmamap_load_raw __P((bus_dma_tag_t, bus_dmamap_t,
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bus_dma_segment_t *, int, bus_size_t, int));
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void _isa_bus_dmamap_unload __P((bus_dma_tag_t, bus_dmamap_t));
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void _isa_bus_dmamap_sync __P((bus_dma_tag_t, bus_dmamap_t,
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bus_addr_t, bus_size_t, int));
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int _isa_bus_dmamem_alloc __P((bus_dma_tag_t, bus_size_t, bus_size_t,
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bus_size_t, bus_dma_segment_t *, int, int *, int));
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int _isa_dma_alloc_bouncebuf __P((bus_dma_tag_t, bus_dmamap_t,
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bus_size_t, int));
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void _isa_dma_free_bouncebuf __P((bus_dma_tag_t, bus_dmamap_t));
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/*
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* Entry points for ISA DMA. These are mostly wrappers around
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* the generic functions that understand how to deal with bounce
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* buffers, if necessary.
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*/
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struct i386_bus_dma_tag isa_bus_dma_tag = {
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ISA_DMA_BOUNCE_THRESHOLD,
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_isa_bus_dmamap_create,
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_isa_bus_dmamap_destroy,
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_isa_bus_dmamap_load,
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_isa_bus_dmamap_load_mbuf,
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_isa_bus_dmamap_load_uio,
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_isa_bus_dmamap_load_raw,
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_isa_bus_dmamap_unload,
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_isa_bus_dmamap_sync,
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_isa_bus_dmamem_alloc,
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_bus_dmamem_free,
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_bus_dmamem_map,
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_bus_dmamem_unmap,
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_bus_dmamem_mmap,
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};
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/*
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* Fill in default interrupt table (in case of spuruious interrupt
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* during configuration of kernel, setup interrupt control unit
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*/
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void
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isa_defaultirq()
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{
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int i;
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/* icu vectors */
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for (i = 0; i < ICU_LEN; i++)
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setgate(&idt[ICU_OFFSET + i].gd, IDTVEC(intr)[i], 0,
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SDT_SYS386IGT, SEL_KPL);
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/* initialize 8259's */
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outb(IO_ICU1, 0x11); /* reset; program device, four bytes */
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outb(IO_ICU1+1, ICU_OFFSET); /* starting at this vector index */
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outb(IO_ICU1+1, 1 << IRQ_SLAVE); /* slave on line 2 */
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#ifdef AUTO_EOI_1
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outb(IO_ICU1+1, 2 | 1); /* auto EOI, 8086 mode */
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#else
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outb(IO_ICU1+1, 1); /* 8086 mode */
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#endif
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outb(IO_ICU1+1, 0xff); /* leave interrupts masked */
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outb(IO_ICU1, 0x68); /* special mask mode (if available) */
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outb(IO_ICU1, 0x0a); /* Read IRR by default. */
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#ifdef REORDER_IRQ
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outb(IO_ICU1, 0xc0 | (3 - 1)); /* pri order 3-7, 0-2 (com2 first) */
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#endif
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outb(IO_ICU2, 0x11); /* reset; program device, four bytes */
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outb(IO_ICU2+1, ICU_OFFSET+8); /* staring at this vector index */
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outb(IO_ICU2+1, IRQ_SLAVE);
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#ifdef AUTO_EOI_2
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outb(IO_ICU2+1, 2 | 1); /* auto EOI, 8086 mode */
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#else
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outb(IO_ICU2+1, 1); /* 8086 mode */
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#endif
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outb(IO_ICU2+1, 0xff); /* leave interrupts masked */
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outb(IO_ICU2, 0x68); /* special mask mode (if available) */
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outb(IO_ICU2, 0x0a); /* Read IRR by default. */
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}
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/*
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* Handle a NMI, possibly a machine check.
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* return true to panic system, false to ignore.
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*/
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int
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isa_nmi()
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{
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log(LOG_CRIT, "NMI port 61 %x, port 70 %x\n", inb(0x61), inb(0x70));
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return(0);
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}
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/*
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* Caught a stray interrupt, notify
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*/
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void
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isa_strayintr(irq)
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int irq;
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{
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static u_long strays;
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/*
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* Stray interrupts on irq 7 occur when an interrupt line is raised
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* and then lowered before the CPU acknowledges it. This generally
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* means either the device is screwed or something is cli'ing too
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* long and it's timing out.
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*/
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if (++strays <= 5)
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log(LOG_ERR, "stray interrupt %d%s\n", irq,
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strays >= 5 ? "; stopped logging" : "");
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}
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int intrtype[ICU_LEN], intrmask[ICU_LEN], intrlevel[ICU_LEN];
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struct intrhand *intrhand[ICU_LEN];
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/*
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* Recalculate the interrupt masks from scratch.
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* We could code special registry and deregistry versions of this function that
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* would be faster, but the code would be nastier, and we don't expect this to
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* happen very much anyway.
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*/
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void
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intr_calculatemasks()
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{
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int irq, level;
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struct intrhand *q;
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/* First, figure out which levels each IRQ uses. */
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for (irq = 0; irq < ICU_LEN; irq++) {
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int levels = 0;
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for (q = intrhand[irq]; q; q = q->ih_next)
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levels |= 1 << q->ih_level;
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intrlevel[irq] = levels;
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}
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/* Then figure out which IRQs use each level. */
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for (level = 0; level < NIPL; level++) {
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int irqs = 0;
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for (irq = 0; irq < ICU_LEN; irq++)
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if (intrlevel[irq] & (1 << level))
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irqs |= 1 << irq;
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imask[level] = irqs;
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}
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/*
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* Initialize soft interrupt masks to block themselves.
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*/
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imask[IPL_SOFTCLOCK] = 1 << SIR_CLOCK;
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imask[IPL_SOFTNET] = 1 << SIR_NET;
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imask[IPL_SOFTSERIAL] = 1 << SIR_SERIAL;
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/*
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* IPL_NONE is used for hardware interrupts that are never blocked,
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* and do not block anything else.
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*/
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imask[IPL_NONE] = 0;
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/*
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* Enforce a hierarchy that gives slow devices a better chance at not
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* dropping data.
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*/
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imask[IPL_SOFTCLOCK] |= imask[IPL_NONE];
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imask[IPL_SOFTNET] |= imask[IPL_SOFTCLOCK];
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imask[IPL_BIO] |= imask[IPL_SOFTNET];
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imask[IPL_NET] |= imask[IPL_BIO];
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imask[IPL_SOFTSERIAL] |= imask[IPL_NET];
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imask[IPL_TTY] |= imask[IPL_SOFTSERIAL];
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/*
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* There are tty, network and disk drivers that use free() at interrupt
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* time, so imp > (tty | net | bio).
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*/
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imask[IPL_IMP] |= imask[IPL_TTY];
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imask[IPL_AUDIO] |= imask[IPL_IMP];
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/*
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* Since run queues may be manipulated by both the statclock and tty,
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* network, and disk drivers, clock > imp.
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*/
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imask[IPL_CLOCK] |= imask[IPL_AUDIO];
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/*
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* IPL_HIGH must block everything that can manipulate a run queue.
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*/
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imask[IPL_HIGH] |= imask[IPL_CLOCK];
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/*
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* We need serial drivers to run at the absolute highest priority to
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* avoid overruns, so serial > high.
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*/
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imask[IPL_SERIAL] |= imask[IPL_HIGH];
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/* And eventually calculate the complete masks. */
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for (irq = 0; irq < ICU_LEN; irq++) {
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int irqs = 1 << irq;
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for (q = intrhand[irq]; q; q = q->ih_next)
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irqs |= imask[q->ih_level];
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intrmask[irq] = irqs;
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}
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/* Lastly, determine which IRQs are actually in use. */
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{
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int irqs = 0;
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for (irq = 0; irq < ICU_LEN; irq++)
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if (intrhand[irq])
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irqs |= 1 << irq;
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if (irqs >= 0x100) /* any IRQs >= 8 in use */
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irqs |= 1 << IRQ_SLAVE;
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imen = ~irqs;
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SET_ICUS();
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}
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}
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int
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fakeintr(arg)
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void *arg;
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{
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return 0;
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}
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#define LEGAL_IRQ(x) ((x) >= 0 && (x) < ICU_LEN && (x) != 2)
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int
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isa_intr_alloc(ic, mask, type, irq)
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isa_chipset_tag_t ic;
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int mask;
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int type;
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int *irq;
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{
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int i, tmp, bestirq, count;
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struct intrhand **p, *q;
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if (type == IST_NONE)
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panic("intr_alloc: bogus type");
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bestirq = -1;
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count = -1;
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/* some interrupts should never be dynamically allocated */
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mask &= 0xdef8;
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/*
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* XXX some interrupts will be used later (6 for fdc, 12 for pms).
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* the right answer is to do "breadth-first" searching of devices.
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*/
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mask &= 0xefbf;
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for (i = 0; i < ICU_LEN; i++) {
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if (LEGAL_IRQ(i) == 0 || (mask & (1<<i)) == 0)
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continue;
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switch(intrtype[i]) {
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case IST_NONE:
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/*
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* if nothing's using the irq, just return it
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*/
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*irq = i;
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return (0);
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case IST_EDGE:
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case IST_LEVEL:
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if (type != intrtype[i])
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continue;
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/*
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* if the irq is shareable, count the number of other
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* handlers, and if it's smaller than the last irq like
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* this, remember it
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*
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* XXX We should probably also consider the
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* interrupt level and stick IPL_TTY with other
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* IPL_TTY, etc.
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*/
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for (p = &intrhand[i], tmp = 0; (q = *p) != NULL;
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p = &q->ih_next, tmp++)
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;
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if ((bestirq == -1) || (count > tmp)) {
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bestirq = i;
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count = tmp;
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}
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break;
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case IST_PULSE:
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/* this just isn't shareable */
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continue;
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}
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}
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if (bestirq == -1)
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return (1);
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*irq = bestirq;
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return (0);
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}
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/*
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* Set up an interrupt handler to start being called.
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* XXX PRONE TO RACE CONDITIONS, UGLY, 'INTERESTING' INSERTION ALGORITHM.
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*/
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void *
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isa_intr_establish(ic, irq, type, level, ih_fun, ih_arg)
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isa_chipset_tag_t ic;
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int irq;
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int type;
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int level;
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int (*ih_fun) __P((void *));
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void *ih_arg;
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{
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struct intrhand **p, *q, *ih;
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static struct intrhand fakehand = {fakeintr};
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extern int cold;
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/* no point in sleeping unless someone can free memory. */
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ih = malloc(sizeof *ih, M_DEVBUF, cold ? M_NOWAIT : M_WAITOK);
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if (ih == NULL)
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panic("isa_intr_establish: can't malloc handler info");
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if (!LEGAL_IRQ(irq) || type == IST_NONE)
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panic("intr_establish: bogus irq or type");
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switch (intrtype[irq]) {
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case IST_NONE:
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intrtype[irq] = type;
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break;
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case IST_EDGE:
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case IST_LEVEL:
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if (type == intrtype[irq])
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break;
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case IST_PULSE:
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if (type != IST_NONE)
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panic("intr_establish: irq %d can't share %s with %s",
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irq,
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isa_intr_typename(intrtype[irq]),
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isa_intr_typename(type));
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break;
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}
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/*
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* Figure out where to put the handler.
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* This is O(N^2), but we want to preserve the order, and N is
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* generally small.
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*/
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for (p = &intrhand[irq]; (q = *p) != NULL; p = &q->ih_next)
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;
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/*
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* Actually install a fake handler momentarily, since we might be doing
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* this with interrupts enabled and don't want the real routine called
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* until masking is set up.
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*/
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fakehand.ih_level = level;
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*p = &fakehand;
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intr_calculatemasks();
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/*
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* Poke the real handler in now.
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*/
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ih->ih_fun = ih_fun;
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ih->ih_arg = ih_arg;
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ih->ih_count = 0;
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ih->ih_next = NULL;
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ih->ih_level = level;
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ih->ih_irq = irq;
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*p = ih;
|
|
|
|
return (ih);
|
|
}
|
|
|
|
/*
|
|
* Deregister an interrupt handler.
|
|
*/
|
|
void
|
|
isa_intr_disestablish(ic, arg)
|
|
isa_chipset_tag_t ic;
|
|
void *arg;
|
|
{
|
|
struct intrhand *ih = arg;
|
|
int irq = ih->ih_irq;
|
|
struct intrhand **p, *q;
|
|
|
|
if (!LEGAL_IRQ(irq))
|
|
panic("intr_disestablish: bogus irq");
|
|
|
|
/*
|
|
* Remove the handler from the chain.
|
|
* This is O(n^2), too.
|
|
*/
|
|
for (p = &intrhand[irq]; (q = *p) != NULL && q != ih; p = &q->ih_next)
|
|
;
|
|
if (q)
|
|
*p = q->ih_next;
|
|
else
|
|
panic("intr_disestablish: handler not registered");
|
|
free(ih, M_DEVBUF);
|
|
|
|
intr_calculatemasks();
|
|
|
|
if (intrhand[irq] == NULL)
|
|
intrtype[irq] = IST_NONE;
|
|
}
|
|
|
|
void
|
|
isa_attach_hook(parent, self, iba)
|
|
struct device *parent, *self;
|
|
struct isabus_attach_args *iba;
|
|
{
|
|
static struct i386_isa_chipset i386_isa_chipset;
|
|
extern int isa_has_been_seen;
|
|
|
|
/*
|
|
* Notify others that might need to know that the ISA bus
|
|
* has now been attached.
|
|
*/
|
|
if (isa_has_been_seen)
|
|
panic("isaattach: ISA bus already seen!");
|
|
isa_has_been_seen = 1;
|
|
|
|
/*
|
|
* Since we can only have one ISA bus, we just use a single
|
|
* statically allocated ISA chipset structure. Pass it up
|
|
* now.
|
|
*/
|
|
iba->iba_ic = &i386_isa_chipset;
|
|
}
|
|
|
|
int
|
|
isa_mem_alloc(t, size, align, boundary, flags, addrp, bshp)
|
|
bus_space_tag_t t;
|
|
bus_size_t size, align;
|
|
bus_addr_t boundary;
|
|
int flags;
|
|
bus_addr_t *addrp;
|
|
bus_space_handle_t *bshp;
|
|
{
|
|
|
|
/*
|
|
* Allocate physical address space in the ISA hole.
|
|
*/
|
|
return (bus_space_alloc(t, IOM_BEGIN, IOM_END - 1, size, align,
|
|
boundary, flags, addrp, bshp));
|
|
}
|
|
|
|
void
|
|
isa_mem_free(t, bsh, size)
|
|
bus_space_tag_t t;
|
|
bus_space_handle_t bsh;
|
|
bus_size_t size;
|
|
{
|
|
|
|
bus_space_free(t, bsh, size);
|
|
}
|
|
|
|
/**********************************************************************
|
|
* bus.h dma interface entry points
|
|
**********************************************************************/
|
|
|
|
#ifdef ISA_DMA_STATS
|
|
#define STAT_INCR(v) (v)++
|
|
#define STAT_DECR(v) do { \
|
|
if ((v) == 0) \
|
|
printf("%s:%d -- Already 0!\n", __FILE__, __LINE__); \
|
|
else \
|
|
(v)--; \
|
|
} while (0)
|
|
u_long isa_dma_stats_loads;
|
|
u_long isa_dma_stats_bounces;
|
|
u_long isa_dma_stats_nbouncebufs;
|
|
#else
|
|
#define STAT_INCR(v)
|
|
#define STAT_DECR(v)
|
|
#endif
|
|
|
|
/*
|
|
* Create an ISA DMA map.
|
|
*/
|
|
int
|
|
_isa_bus_dmamap_create(t, size, nsegments, maxsegsz, boundary, flags, dmamp)
|
|
bus_dma_tag_t t;
|
|
bus_size_t size;
|
|
int nsegments;
|
|
bus_size_t maxsegsz;
|
|
bus_size_t boundary;
|
|
int flags;
|
|
bus_dmamap_t *dmamp;
|
|
{
|
|
struct i386_isa_dma_cookie *cookie;
|
|
bus_dmamap_t map;
|
|
int error, cookieflags;
|
|
void *cookiestore;
|
|
size_t cookiesize;
|
|
|
|
/* Call common function to create the basic map. */
|
|
error = _bus_dmamap_create(t, size, nsegments, maxsegsz, boundary,
|
|
flags, dmamp);
|
|
if (error)
|
|
return (error);
|
|
|
|
map = *dmamp;
|
|
map->_dm_cookie = NULL;
|
|
|
|
cookiesize = sizeof(struct i386_isa_dma_cookie);
|
|
|
|
/*
|
|
* ISA only has 24-bits of address space. This means
|
|
* we can't DMA to pages over 16M. In order to DMA to
|
|
* arbitrary buffers, we use "bounce buffers" - pages
|
|
* in memory below the 16M boundary. On DMA reads,
|
|
* DMA happens to the bounce buffers, and is copied into
|
|
* the caller's buffer. On writes, data is copied into
|
|
* but bounce buffer, and the DMA happens from those
|
|
* pages. To software using the DMA mapping interface,
|
|
* this looks simply like a data cache.
|
|
*
|
|
* If we have more than 16M of RAM in the system, we may
|
|
* need bounce buffers. We check and remember that here.
|
|
*
|
|
* There are exceptions, however. VLB devices can do
|
|
* 32-bit DMA, and indicate that here.
|
|
*
|
|
* ...or, there is an opposite case. The most segments
|
|
* a transfer will require is (maxxfer / NBPG) + 1. If
|
|
* the caller can't handle that many segments (e.g. the
|
|
* ISA DMA controller), we may have to bounce it as well.
|
|
*/
|
|
cookieflags = 0;
|
|
if ((avail_end > ISA_DMA_BOUNCE_THRESHOLD &&
|
|
(flags & ISABUS_DMA_32BIT) == 0) ||
|
|
((map->_dm_size / NBPG) + 1) > map->_dm_segcnt) {
|
|
cookieflags |= ID_MIGHT_NEED_BOUNCE;
|
|
cookiesize += (sizeof(bus_dma_segment_t) * map->_dm_segcnt);
|
|
}
|
|
|
|
/*
|
|
* Allocate our cookie.
|
|
*/
|
|
if ((cookiestore = malloc(cookiesize, M_DMAMAP,
|
|
(flags & BUS_DMA_NOWAIT) ? M_NOWAIT : M_WAITOK)) == NULL) {
|
|
error = ENOMEM;
|
|
goto out;
|
|
}
|
|
memset(cookiestore, 0, cookiesize);
|
|
cookie = (struct i386_isa_dma_cookie *)cookiestore;
|
|
cookie->id_flags = cookieflags;
|
|
map->_dm_cookie = cookie;
|
|
|
|
if (cookieflags & ID_MIGHT_NEED_BOUNCE) {
|
|
/*
|
|
* Allocate the bounce pages now if the caller
|
|
* wishes us to do so.
|
|
*/
|
|
if ((flags & BUS_DMA_ALLOCNOW) == 0)
|
|
goto out;
|
|
|
|
error = _isa_dma_alloc_bouncebuf(t, map, size, flags);
|
|
}
|
|
|
|
out:
|
|
if (error) {
|
|
if (map->_dm_cookie != NULL)
|
|
free(map->_dm_cookie, M_DMAMAP);
|
|
_bus_dmamap_destroy(t, map);
|
|
}
|
|
return (error);
|
|
}
|
|
|
|
/*
|
|
* Destroy an ISA DMA map.
|
|
*/
|
|
void
|
|
_isa_bus_dmamap_destroy(t, map)
|
|
bus_dma_tag_t t;
|
|
bus_dmamap_t map;
|
|
{
|
|
struct i386_isa_dma_cookie *cookie = map->_dm_cookie;
|
|
|
|
/*
|
|
* Free any bounce pages this map might hold.
|
|
*/
|
|
if (cookie->id_flags & ID_HAS_BOUNCE)
|
|
_isa_dma_free_bouncebuf(t, map);
|
|
|
|
free(cookie, M_DMAMAP);
|
|
_bus_dmamap_destroy(t, map);
|
|
}
|
|
|
|
/*
|
|
* Load an ISA DMA map with a linear buffer.
|
|
*/
|
|
int
|
|
_isa_bus_dmamap_load(t, map, buf, buflen, p, flags)
|
|
bus_dma_tag_t t;
|
|
bus_dmamap_t map;
|
|
void *buf;
|
|
bus_size_t buflen;
|
|
struct proc *p;
|
|
int flags;
|
|
{
|
|
struct i386_isa_dma_cookie *cookie = map->_dm_cookie;
|
|
int error;
|
|
|
|
STAT_INCR(isa_dma_stats_loads);
|
|
|
|
/*
|
|
* Make sure that on error condition we return "no valid mappings."
|
|
*/
|
|
map->dm_mapsize = 0;
|
|
map->dm_nsegs = 0;
|
|
|
|
/*
|
|
* Try to load the map the normal way. If this errors out,
|
|
* and we can bounce, we will.
|
|
*/
|
|
error = _bus_dmamap_load(t, map, buf, buflen, p, flags);
|
|
if (error == 0 ||
|
|
(error != 0 && (cookie->id_flags & ID_MIGHT_NEED_BOUNCE) == 0))
|
|
return (error);
|
|
|
|
/*
|
|
* First attempt failed; bounce it.
|
|
*/
|
|
|
|
STAT_INCR(isa_dma_stats_bounces);
|
|
|
|
/*
|
|
* Allocate bounce pages, if necessary.
|
|
*/
|
|
if ((cookie->id_flags & ID_HAS_BOUNCE) == 0) {
|
|
error = _isa_dma_alloc_bouncebuf(t, map, buflen, flags);
|
|
if (error)
|
|
return (error);
|
|
}
|
|
|
|
/*
|
|
* Cache a pointer to the caller's buffer and load the DMA map
|
|
* with the bounce buffer.
|
|
*/
|
|
cookie->id_origbuf = buf;
|
|
cookie->id_origbuflen = buflen;
|
|
cookie->id_buftype = ID_BUFTYPE_LINEAR;
|
|
error = _bus_dmamap_load(t, map, cookie->id_bouncebuf, buflen,
|
|
p, flags);
|
|
if (error) {
|
|
/*
|
|
* Free the bounce pages, unless our resources
|
|
* are reserved for our exclusive use.
|
|
*/
|
|
if ((map->_dm_flags & BUS_DMA_ALLOCNOW) == 0)
|
|
_isa_dma_free_bouncebuf(t, map);
|
|
return (error);
|
|
}
|
|
|
|
/* ...so _isa_bus_dmamap_sync() knows we're bouncing */
|
|
cookie->id_flags |= ID_IS_BOUNCING;
|
|
return (0);
|
|
}
|
|
|
|
/*
|
|
* Like _isa_bus_dmamap_load(), but for mbufs.
|
|
*/
|
|
int
|
|
_isa_bus_dmamap_load_mbuf(t, map, m0, flags)
|
|
bus_dma_tag_t t;
|
|
bus_dmamap_t map;
|
|
struct mbuf *m0;
|
|
int flags;
|
|
{
|
|
struct i386_isa_dma_cookie *cookie = map->_dm_cookie;
|
|
int error;
|
|
|
|
/*
|
|
* Make sure on error condition we return "no valid mappings."
|
|
*/
|
|
map->dm_mapsize = 0;
|
|
map->dm_nsegs = 0;
|
|
|
|
#ifdef DIAGNOSTIC
|
|
if ((m0->m_flags & M_PKTHDR) == 0)
|
|
panic("_isa_bus_dmamap_load_mbuf: no packet header");
|
|
#endif
|
|
|
|
if (m0->m_pkthdr.len > map->_dm_size)
|
|
return (EINVAL);
|
|
|
|
/*
|
|
* Try to load the map the normal way. If this errors out,
|
|
* and we can bounce, we will.
|
|
*/
|
|
error = _bus_dmamap_load_mbuf(t, map, m0, flags);
|
|
if (error == 0 ||
|
|
(error != 0 && (cookie->id_flags & ID_MIGHT_NEED_BOUNCE) == 0))
|
|
return (error);
|
|
|
|
/*
|
|
* First attempt failed; bounce it.
|
|
*/
|
|
|
|
STAT_INCR(isa_dma_stats_bounces);
|
|
|
|
/*
|
|
* Allocate bounce pages, if necessary.
|
|
*/
|
|
if ((cookie->id_flags & ID_HAS_BOUNCE) == 0) {
|
|
error = _isa_dma_alloc_bouncebuf(t, map, m0->m_pkthdr.len,
|
|
flags);
|
|
if (error)
|
|
return (error);
|
|
}
|
|
|
|
/*
|
|
* Cache a pointer to the caller's buffer and load the DMA map
|
|
* with the bounce buffer.
|
|
*/
|
|
cookie->id_origbuf = m0;
|
|
cookie->id_origbuflen = m0->m_pkthdr.len; /* not really used */
|
|
cookie->id_buftype = ID_BUFTYPE_MBUF;
|
|
error = _bus_dmamap_load(t, map, cookie->id_bouncebuf,
|
|
m0->m_pkthdr.len, NULL, flags);
|
|
if (error) {
|
|
/*
|
|
* Free the bounce pages, unless our resources
|
|
* are reserved for our exclusive use.
|
|
*/
|
|
if ((map->_dm_flags & BUS_DMA_ALLOCNOW) == 0)
|
|
_isa_dma_free_bouncebuf(t, map);
|
|
return (error);
|
|
}
|
|
|
|
/* ...so _isa_bus_dmamap_sync() knows we're bouncing */
|
|
cookie->id_flags |= ID_IS_BOUNCING;
|
|
return (0);
|
|
}
|
|
|
|
/*
|
|
* Like _isa_bus_dmamap_load(), but for uios.
|
|
*/
|
|
int
|
|
_isa_bus_dmamap_load_uio(t, map, uio, flags)
|
|
bus_dma_tag_t t;
|
|
bus_dmamap_t map;
|
|
struct uio *uio;
|
|
int flags;
|
|
{
|
|
|
|
panic("_isa_bus_dmamap_load_uio: not implemented");
|
|
}
|
|
|
|
/*
|
|
* Like _isa_bus_dmamap_load(), but for raw memory allocated with
|
|
* bus_dmamem_alloc().
|
|
*/
|
|
int
|
|
_isa_bus_dmamap_load_raw(t, map, segs, nsegs, size, flags)
|
|
bus_dma_tag_t t;
|
|
bus_dmamap_t map;
|
|
bus_dma_segment_t *segs;
|
|
int nsegs;
|
|
bus_size_t size;
|
|
int flags;
|
|
{
|
|
|
|
panic("_isa_bus_dmamap_load_raw: not implemented");
|
|
}
|
|
|
|
/*
|
|
* Unload an ISA DMA map.
|
|
*/
|
|
void
|
|
_isa_bus_dmamap_unload(t, map)
|
|
bus_dma_tag_t t;
|
|
bus_dmamap_t map;
|
|
{
|
|
struct i386_isa_dma_cookie *cookie = map->_dm_cookie;
|
|
|
|
/*
|
|
* If we have bounce pages, free them, unless they're
|
|
* reserved for our exclusive use.
|
|
*/
|
|
if ((cookie->id_flags & ID_HAS_BOUNCE) &&
|
|
(map->_dm_flags & BUS_DMA_ALLOCNOW) == 0)
|
|
_isa_dma_free_bouncebuf(t, map);
|
|
|
|
cookie->id_flags &= ~ID_IS_BOUNCING;
|
|
cookie->id_buftype = ID_BUFTYPE_INVALID;
|
|
|
|
/*
|
|
* Do the generic bits of the unload.
|
|
*/
|
|
_bus_dmamap_unload(t, map);
|
|
}
|
|
|
|
/*
|
|
* Synchronize an ISA DMA map.
|
|
*/
|
|
void
|
|
_isa_bus_dmamap_sync(t, map, offset, len, ops)
|
|
bus_dma_tag_t t;
|
|
bus_dmamap_t map;
|
|
bus_addr_t offset;
|
|
bus_size_t len;
|
|
int ops;
|
|
{
|
|
struct i386_isa_dma_cookie *cookie = map->_dm_cookie;
|
|
|
|
/*
|
|
* Mixing PRE and POST operations is not allowed.
|
|
*/
|
|
if ((ops & (BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE)) != 0 &&
|
|
(ops & (BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE)) != 0)
|
|
panic("_isa_bus_dmamap_sync: mix PRE and POST");
|
|
|
|
#ifdef DIAGNOSTIC
|
|
if ((ops & (BUS_DMASYNC_PREWRITE|BUS_DMASYNC_POSTREAD)) != 0) {
|
|
if (offset >= map->dm_mapsize)
|
|
panic("_isa_bus_dmamap_sync: bad offset");
|
|
if (len == 0 || (offset + len) > map->dm_mapsize)
|
|
panic("_isa_bus_dmamap_sync: bad length");
|
|
}
|
|
#endif
|
|
|
|
/*
|
|
* If we're not bouncing, just return; nothing to do.
|
|
*/
|
|
if ((cookie->id_flags & ID_IS_BOUNCING) == 0)
|
|
return;
|
|
|
|
switch (cookie->id_buftype) {
|
|
case ID_BUFTYPE_LINEAR:
|
|
/*
|
|
* Nothing to do for pre-read.
|
|
*/
|
|
|
|
if (ops & BUS_DMASYNC_PREWRITE) {
|
|
/*
|
|
* Copy the caller's buffer to the bounce buffer.
|
|
*/
|
|
memcpy(cookie->id_bouncebuf + offset,
|
|
cookie->id_origbuf + offset, len);
|
|
}
|
|
|
|
if (ops & BUS_DMASYNC_POSTREAD) {
|
|
/*
|
|
* Copy the bounce buffer to the caller's buffer.
|
|
*/
|
|
memcpy(cookie->id_origbuf + offset,
|
|
cookie->id_bouncebuf + offset, len);
|
|
}
|
|
|
|
/*
|
|
* Nothing to do for post-write.
|
|
*/
|
|
break;
|
|
|
|
case ID_BUFTYPE_MBUF:
|
|
{
|
|
struct mbuf *m, *m0 = cookie->id_origbuf;
|
|
bus_size_t minlen, moff;
|
|
|
|
/*
|
|
* Nothing to do for pre-read.
|
|
*/
|
|
|
|
if (ops & BUS_DMASYNC_PREWRITE) {
|
|
/*
|
|
* Copy the caller's buffer to the bounce buffer.
|
|
*/
|
|
m_copydata(m0, offset, len,
|
|
cookie->id_bouncebuf + offset);
|
|
}
|
|
|
|
if (ops & BUS_DMASYNC_POSTREAD) {
|
|
/*
|
|
* Copy the bounce buffer to the caller's buffer.
|
|
*/
|
|
for (moff = offset, m = m0; m != NULL && len != 0;
|
|
m = m->m_next) {
|
|
/* Find the beginning mbuf. */
|
|
if (moff >= m->m_len) {
|
|
moff -= m->m_len;
|
|
continue;
|
|
}
|
|
|
|
/*
|
|
* Now at the first mbuf to sync; nail
|
|
* each one until we have exhausted the
|
|
* length.
|
|
*/
|
|
minlen = len < m->m_len - moff ?
|
|
len : m->m_len - moff;
|
|
|
|
memcpy(mtod(m, caddr_t) + moff,
|
|
cookie->id_bouncebuf + offset, minlen);
|
|
|
|
moff = 0;
|
|
len -= minlen;
|
|
offset += minlen;
|
|
}
|
|
}
|
|
|
|
/*
|
|
* Nothing to do for post-write.
|
|
*/
|
|
break;
|
|
}
|
|
|
|
case ID_BUFTYPE_UIO:
|
|
panic("_isa_bus_dmamap_sync: ID_BUFTYPE_UIO");
|
|
break;
|
|
|
|
case ID_BUFTYPE_RAW:
|
|
panic("_isa_bus_dmamap_sync: ID_BUFTYPE_RAW");
|
|
break;
|
|
|
|
case ID_BUFTYPE_INVALID:
|
|
panic("_isa_bus_dmamap_sync: ID_BUFTYPE_INVALID");
|
|
break;
|
|
|
|
default:
|
|
printf("unknown buffer type %d\n", cookie->id_buftype);
|
|
panic("_isa_bus_dmamap_sync");
|
|
}
|
|
}
|
|
|
|
/*
|
|
* Allocate memory safe for ISA DMA.
|
|
*/
|
|
int
|
|
_isa_bus_dmamem_alloc(t, size, alignment, boundary, segs, nsegs, rsegs, flags)
|
|
bus_dma_tag_t t;
|
|
bus_size_t size, alignment, boundary;
|
|
bus_dma_segment_t *segs;
|
|
int nsegs;
|
|
int *rsegs;
|
|
int flags;
|
|
{
|
|
vm_offset_t high;
|
|
|
|
if (avail_end > ISA_DMA_BOUNCE_THRESHOLD)
|
|
high = trunc_page(ISA_DMA_BOUNCE_THRESHOLD);
|
|
else
|
|
high = trunc_page(avail_end);
|
|
|
|
return (_bus_dmamem_alloc_range(t, size, alignment, boundary,
|
|
segs, nsegs, rsegs, flags, 0, high));
|
|
}
|
|
|
|
/**********************************************************************
|
|
* ISA DMA utility functions
|
|
**********************************************************************/
|
|
|
|
int
|
|
_isa_dma_alloc_bouncebuf(t, map, size, flags)
|
|
bus_dma_tag_t t;
|
|
bus_dmamap_t map;
|
|
bus_size_t size;
|
|
int flags;
|
|
{
|
|
struct i386_isa_dma_cookie *cookie = map->_dm_cookie;
|
|
int error = 0;
|
|
|
|
cookie->id_bouncebuflen = round_page(size);
|
|
error = _isa_bus_dmamem_alloc(t, cookie->id_bouncebuflen,
|
|
NBPG, map->_dm_boundary, cookie->id_bouncesegs,
|
|
map->_dm_segcnt, &cookie->id_nbouncesegs, flags);
|
|
if (error)
|
|
goto out;
|
|
error = _bus_dmamem_map(t, cookie->id_bouncesegs,
|
|
cookie->id_nbouncesegs, cookie->id_bouncebuflen,
|
|
(caddr_t *)&cookie->id_bouncebuf, flags);
|
|
|
|
out:
|
|
if (error) {
|
|
_bus_dmamem_free(t, cookie->id_bouncesegs,
|
|
cookie->id_nbouncesegs);
|
|
cookie->id_bouncebuflen = 0;
|
|
cookie->id_nbouncesegs = 0;
|
|
} else {
|
|
cookie->id_flags |= ID_HAS_BOUNCE;
|
|
STAT_INCR(isa_dma_stats_nbouncebufs);
|
|
}
|
|
|
|
return (error);
|
|
}
|
|
|
|
void
|
|
_isa_dma_free_bouncebuf(t, map)
|
|
bus_dma_tag_t t;
|
|
bus_dmamap_t map;
|
|
{
|
|
struct i386_isa_dma_cookie *cookie = map->_dm_cookie;
|
|
|
|
STAT_DECR(isa_dma_stats_nbouncebufs);
|
|
|
|
_bus_dmamem_unmap(t, cookie->id_bouncebuf,
|
|
cookie->id_bouncebuflen);
|
|
_bus_dmamem_free(t, cookie->id_bouncesegs,
|
|
cookie->id_nbouncesegs);
|
|
cookie->id_bouncebuflen = 0;
|
|
cookie->id_nbouncesegs = 0;
|
|
cookie->id_flags &= ~ID_HAS_BOUNCE;
|
|
}
|