379c9be4a8
* commit isapnpvar.h changes required for ARC to support plain isa.
* fixup mistake over mips/include/cpuregs.h.
* mips/mips_machdep.c:
set L2 cache-size for arc, cleanup use of L2cache present
vs L2 cache-size variables. check for no L2 cache on kernels
configured to require one. misc cleanups.
* mips/mpis/trap.c: more locore stack-traceback label cleanup.
XXX Locore callbacks for mips3, mips4, r4600 cacheflush need more work.
98 lines
3.8 KiB
C
98 lines
3.8 KiB
C
/* $NetBSD: trap.h,v 1.9 1998/10/01 00:42:37 jonathan Exp $ */
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/*
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* Copyright (c) 1988 University of Utah.
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* Copyright (c) 1992, 1993
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* The Regents of the University of California. All rights reserved.
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*
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* This code is derived from software contributed to Berkeley by
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* the Systems Programming Group of the University of Utah Computer
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* Science Department and Ralph Campbell.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the University of
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* California, Berkeley and its contributors.
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* 4. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* from: Utah Hdr: trap.h 1.1 90/07/09
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*
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* @(#)trap.h 8.1 (Berkeley) 6/10/93
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*/
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/*
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* special trap-handling support
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*/
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/* Return the resulting PC as if the branch was executed. */
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extern u_int MachEmulateBranch __P((u_int* regs, u_int instPC,
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u_int fpcCSR, int allowNonBranch));
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#ifdef DEBUG
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extern int cpu_singlestep __P((register struct proc *p));
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extern int kdbpeek __P((vm_offset_t addr));
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#endif
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/*
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* Trap codes
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* also known in trap.c for name strings
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*/
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#define T_INT 0 /* Interrupt pending */
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#define T_TLB_MOD 1 /* TLB modified fault */
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#define T_TLB_LD_MISS 2 /* TLB miss on load or ifetch */
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#define T_TLB_ST_MISS 3 /* TLB miss on a store */
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#define T_ADDR_ERR_LD 4 /* Address error on a load or ifetch */
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#define T_ADDR_ERR_ST 5 /* Address error on a store */
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#define T_BUS_ERR_IFETCH 6 /* Bus error on an ifetch */
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#define T_BUS_ERR_LD_ST 7 /* Bus error on a load or store */
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#define T_SYSCALL 8 /* System call */
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#define T_BREAK 9 /* Breakpoint */
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#define T_RES_INST 10 /* Reserved instruction exception */
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#define T_COP_UNUSABLE 11 /* Coprocessor unusable */
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#define T_OVFLOW 12 /* Arithmetic overflow */
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/*
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* Trap definitions added for r4000 port.
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*/
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#define T_TRAP 13 /* Trap instruction */
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#define T_VCEI 14 /* Virtual coherency instruction */
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#define T_FPE 15 /* Floating point exception */
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#define T_WATCH 23 /* Watch address reference */
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#define T_VCED 31 /* Virtual coherency data */
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#define T_USER 0x20 /* user-mode flag or'ed with type */
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#ifdef _KERNEL
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extern int (*mips_hardware_intr) __P((u_int mask, u_int pc, u_int statusReg,
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u_int causeReg));
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#endif /* _KERNEL */
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#ifdef _KERNEL
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extern int (*mips_hardware_intr) __P((u_int mask, u_int pc, u_int statusReg,
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u_int causeReg));
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#endif /* _KERNEL */
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