594 lines
16 KiB
C
594 lines
16 KiB
C
/* $NetBSD: npx.c,v 1.36 1995/05/01 04:47:43 mycroft Exp $ */
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#if 0
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#define iprintf(x) printf x
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#else
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#define iprintf(x)
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#endif
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/*-
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* Copyright (c) 1994, 1995 Charles M. Hannum. All rights reserved.
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* Copyright (c) 1990 William Jolitz.
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* Copyright (c) 1991 The Regents of the University of California.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the University of
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* California, Berkeley and its contributors.
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* 4. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* @(#)npx.c 7.2 (Berkeley) 5/12/91
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*/
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/conf.h>
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#include <sys/file.h>
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#include <sys/proc.h>
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#include <sys/user.h>
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#include <sys/ioctl.h>
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#include <sys/device.h>
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#include <machine/cpu.h>
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#include <machine/pio.h>
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#include <machine/cpufunc.h>
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#include <machine/pcb.h>
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#include <machine/trap.h>
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#include <machine/specialreg.h>
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#include <i386/isa/icu.h>
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#include <dev/isa/isavar.h>
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#include <dev/isa/isareg.h>
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/*
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* 387 and 287 Numeric Coprocessor Extension (NPX) Driver.
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*
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* We do lazy initialization and switching using the TS and EM bits in cr0.
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* DNA exceptions are handled like this:
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*
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* 1) If someone else has used the NPX, save its state into that process's PCB.
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* 2) If the EM bit is set, then
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* a) if no NPX is present, return and go to the emulator.
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* b) if a NPX is present, turn off the EM bit and initialize the NPX.
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* 3) If the EM bit is not set, reload the process's previous NPX state.
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*
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* The actual ordering is slightly different for performance reasons.
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*
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* When a process is created or exec()s, its saved cr0 image has both the EM
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* and TS bits sets. The EM bit is turned off when it first gets a DNA and the
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* NPX is initialized. The TS bit is turned off when the NPX is used, and
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* turned on again later when the process's NPX state is saved.
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*/
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#define fldcw(addr) __asm("fldcw %0" : : "m" (*addr))
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#define fnclex() __asm("fnclex")
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#define fninit() __asm("fninit")
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#define fnsave(addr) __asm("fnsave %0" : "=m" (*addr) : "0" (*addr))
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#define fnstcw(addr) __asm("fnstcw %0" : "=m" (*addr) : "0" (*addr))
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#define fnstsw(addr) __asm("fnstsw %0" : "=m" (*addr) : "0" (*addr))
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#define fp_divide_by_0() __asm("fldz; fld1; fdiv %st,%st(1); fwait")
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#define frstor(addr) __asm("frstor %0" : : "m" (*addr))
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#define fwait() __asm("fwait")
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#define read_eflags() ({register u_long ef; \
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__asm("pushfl; popl %0" : "=r" (ef)); \
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ef;})
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#define write_eflags(x) ({register u_long ef = (x); \
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__asm("pushl %0; popfl" : : "r" (ef));})
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#define clts() __asm("clts")
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#define stts() lcr0(rcr0() | CR0_TS)
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int npxdna __P((void));
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void npxexit __P((void));
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void npxinit __P((void));
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int npxintr __P((void *));
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static int npxprobe1 __P((struct isa_attach_args *));
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void npxsave __P((void));
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static void npxsave1 __P((void));
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struct npx_softc {
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struct device sc_dev;
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void *sc_ih;
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};
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int npxprobe __P((struct device *, void *, void *));
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void npxattach __P((struct device *, struct device *, void *));
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struct cfdriver npxcd = {
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NULL, "npx", npxprobe, npxattach, DV_DULL, sizeof(struct npx_softc)
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};
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enum npx_type {
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NPX_NONE = 0,
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NPX_INTERRUPT,
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NPX_EXCEPTION,
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NPX_BROKEN,
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};
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struct proc *npxproc;
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static enum npx_type npx_type;
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static int npx_nointr;
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static volatile u_int npx_intrs_while_probing;
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static volatile u_int npx_traps_while_probing;
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/*
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* Special interrupt handlers. Someday intr0-intr15 will be used to count
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* interrupts. We'll still need a special exception 16 handler. The busy
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* latch stuff in probintr() can be moved to npxprobe().
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*/
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void probeintr __P((void));
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asm ("
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.text
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_probeintr:
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ss
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incl _npx_intrs_while_probing
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pushl %eax
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movb $0x20,%al # EOI (asm in strings loses cpp features)
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outb %al,$0xa0 # IO_ICU2
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outb %al,$0x20 # IO_ICU1
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movb $0,%al
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outb %al,$0xf0 # clear BUSY# latch
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popl %eax
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iret
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");
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void probetrap __P((void));
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asm ("
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.text
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_probetrap:
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ss
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incl _npx_traps_while_probing
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fnclex
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iret
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");
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static inline int
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npxprobe1(ia)
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struct isa_attach_args *ia;
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{
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int control;
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int status;
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ia->ia_iosize = 16;
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ia->ia_msize = 0;
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/*
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* Finish resetting the coprocessor, if any. If there is an error
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* pending, then we may get a bogus IRQ13, but probeintr() will handle
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* it OK. Bogus halts have never been observed, but we enabled
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* IRQ13 and cleared the BUSY# latch early to handle them anyway.
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*/
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fninit();
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delay(1000); /* wait for any IRQ13 (fwait might hang) */
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/*
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* Check for a status of mostly zero.
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*/
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status = 0x5a5a;
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fnstsw(&status);
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if ((status & 0xb8ff) == 0) {
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/*
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* Good, now check for a proper control word.
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*/
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control = 0x5a5a;
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fnstcw(&control);
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if ((control & 0x1f3f) == 0x033f) {
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/*
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* We have an npx, now divide by 0 to see if exception
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* 16 works.
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*/
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control &= ~(1 << 2); /* enable divide by 0 trap */
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fldcw(&control);
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npx_traps_while_probing = npx_intrs_while_probing = 0;
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fp_divide_by_0();
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if (npx_traps_while_probing != 0) {
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/*
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* Good, exception 16 works.
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*/
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npx_type = NPX_EXCEPTION;
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ia->ia_irq = IRQUNK; /* zap the interrupt */
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} else if (npx_intrs_while_probing != 0) {
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/*
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* Bad, we are stuck with IRQ13.
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*/
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npx_type = NPX_INTERRUPT;
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} else {
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/*
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* Worse, even IRQ13 is broken. Use emulator.
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*/
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npx_type = NPX_BROKEN;
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ia->ia_irq = IRQUNK;
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}
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return 1;
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}
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}
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/*
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* Probe failed. There is no usable FPU.
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*/
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npx_type = NPX_NONE;
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return 0;
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}
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/*
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* Probe routine. Initialize cr0 to give correct behaviour for [f]wait
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* whether the device exists or not (XXX should be elsewhere). Set flags
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* to tell npxattach() what to do. Modify device struct if npx doesn't
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* need to use interrupts. Return 1 if device exists.
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*/
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int
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npxprobe(parent, match, aux)
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struct device *parent;
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void *match, *aux;
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{
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struct isa_attach_args *ia = aux;
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int irq;
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int result;
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u_long save_eflags;
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unsigned save_imen;
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struct gate_descriptor save_idt_npxintr;
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struct gate_descriptor save_idt_npxtrap;
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/*
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* This routine is now just a wrapper for npxprobe1(), to install
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* special npx interrupt and trap handlers, to enable npx interrupts
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* and to disable other interrupts. Someday isa_configure() will
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* install suitable handlers and run with interrupts enabled so we
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* won't need to do so much here.
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*/
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irq = NRSVIDT + ia->ia_irq;
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save_eflags = read_eflags();
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disable_intr();
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save_idt_npxintr = idt[irq];
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save_idt_npxtrap = idt[16];
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setgate(&idt[irq], probeintr, 0, SDT_SYS386IGT, SEL_KPL);
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setgate(&idt[16], probetrap, 0, SDT_SYS386TGT, SEL_KPL);
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save_imen = imen;
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imen = ~((1 << IRQ_SLAVE) | (1 << ia->ia_irq));
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SET_ICUS();
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/*
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* Partially reset the coprocessor, if any. Some BIOS's don't reset
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* it after a warm boot.
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*/
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outb(0xf1, 0); /* full reset on some systems, NOP on others */
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delay(1000);
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outb(0xf0, 0); /* clear BUSY# latch */
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/*
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* We set CR0 in locore to trap all ESC and WAIT instructions.
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* We have to turn off the CR0_EM bit temporarily while probing.
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*/
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lcr0(rcr0() & ~(CR0_EM|CR0_TS));
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enable_intr();
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result = npxprobe1(ia);
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disable_intr();
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lcr0(rcr0() | (CR0_EM|CR0_TS));
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imen = save_imen;
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SET_ICUS();
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idt[irq] = save_idt_npxintr;
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idt[16] = save_idt_npxtrap;
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write_eflags(save_eflags);
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return (result);
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}
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int npx586bug1 __P((int, int));
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asm ("
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.text
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_npx586bug1:
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fildl 4(%esp) # x
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fildl 8(%esp) # y
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fld %st(1)
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fdiv %st(1),%st # x/y
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fmulp %st,%st(1) # (x/y)*y
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fsubrp %st,%st(1) # x-(x/y)*y
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pushl $0
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fistpl (%esp)
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popl %eax
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ret
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");
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/*
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* Attach routine - announce which it is, and wire into system
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*/
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void
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npxattach(parent, self, aux)
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struct device *parent, *self;
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void *aux;
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{
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struct npx_softc *sc = (void *)self;
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struct isa_attach_args *ia = aux;
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switch (npx_type) {
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case NPX_INTERRUPT:
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printf("\n");
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sc->sc_ih = isa_intr_establish(ia->ia_irq, ISA_IST_EDGE,
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ISA_IPL_NONE, npxintr, 0);
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break;
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case NPX_EXCEPTION:
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printf(": using exception 16\n");
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break;
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case NPX_BROKEN:
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printf(": error reporting broken; not using\n");
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npx_type = NPX_NONE;
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return;
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}
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lcr0(rcr0() & ~(CR0_EM|CR0_TS));
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fninit();
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if (npx586bug1(4195835, 3145727) != 0)
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printf("WARNING: Pentium FDIV bug detected!\n");
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lcr0(rcr0() | (CR0_EM|CR0_TS));
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}
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/*
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* Record the FPU state and reinitialize it all except for the control word.
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* Then generate a SIGFPE.
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*
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* Reinitializing the state allows naive SIGFPE handlers to longjmp without
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* doing any fixups.
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*
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* XXX there is currently no way to pass the full error state to signal
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* handlers, and if this is a nested interrupt there is no way to pass even
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* a status code! So there is no way to have a non-naive SIGFPE handler. At
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* best a handler could do an fninit followed by an fldcw of a static value.
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* fnclex would be of little use because it would leave junk on the FPU stack.
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* Returning from the handler would be even less safe than usual because
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* IRQ13 exception handling makes exceptions even less precise than usual.
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*/
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int
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npxintr(arg)
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void *arg;
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{
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register struct proc *p = npxproc;
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register struct save87 *addr;
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struct intrframe *frame = arg;
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int code;
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cnt.v_trap++;
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iprintf(("Intr"));
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if (p == 0 || npx_type == NPX_NONE) {
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/* XXX no %p in stand/printf.c. Cast to quiet gcc -Wall. */
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printf("npxintr: p = %lx, curproc = %lx, npx_type = %d\n",
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(u_long) p, (u_long) curproc, npx_type);
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panic("npxintr from nowhere");
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}
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/*
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* Clear the interrupt latch.
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*/
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outb(0xf0, 0);
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/*
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* If we're saving, ignore the interrupt. The FPU will happily
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* generate another one when we restore the state later.
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*/
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if (npx_nointr != 0)
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return (1);
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/*
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* Find the address of npxproc's savefpu. This is not necessarily
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* the one in curpcb.
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*/
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addr = &p->p_addr->u_pcb.pcb_savefpu;
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/*
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* Save state. This does an implied fninit. It had better not halt
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* the cpu or we'll hang.
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*/
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fnsave(addr);
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fwait();
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/*
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* Restore control word (was clobbered by fnsave).
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*/
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fldcw(&addr->sv_env.en_cw);
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fwait();
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/*
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* Remember the exception status word and tag word. The current
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* (almost fninit'ed) fpu state is in the fpu and the exception
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* state just saved will soon be junk. However, the implied fninit
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* doesn't change the error pointers or register contents, and we
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* preserved the control word and will copy the status and tag
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* words, so the complete exception state can be recovered.
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*/
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addr->sv_ex_sw = addr->sv_env.en_sw;
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addr->sv_ex_tw = addr->sv_env.en_tw;
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/*
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* Pass exception to process. If it's the current process, try to do
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* it immediately.
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*/
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if (p == curproc && ISPL(frame->if_cs) == SEL_UPL) {
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/*
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* Interrupt is essentially a trap, so we can afford to call
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* the SIGFPE handler (if any) as soon as the interrupt
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* returns.
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*
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* XXX little or nothing is gained from this, and plenty is
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* lost - the interrupt frame has to contain the trap frame
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* (this is otherwise only necessary for the rescheduling trap
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* in doreti, and the frame for that could easily be set up
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* just before it is used).
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*/
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p->p_md.md_regs = (int *)&frame->if_es;
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#ifdef notyet
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/*
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* Encode the appropriate code for detailed information on
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* this exception.
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*/
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code = XXX_ENCODE(addr->sv_ex_sw);
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#else
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code = 0; /* XXX */
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#endif
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trapsignal(p, SIGFPE, code);
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} else {
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/*
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* Nested interrupt. These losers occur when:
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* o an IRQ13 is bogusly generated at a bogus time, e.g.:
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* o immediately after an fnsave or frstor of an
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* error state.
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* o a couple of 386 instructions after
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* "fstpl _memvar" causes a stack overflow.
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* These are especially nasty when combined with a
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* trace trap.
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* o an IRQ13 occurs at the same time as another higher-
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* priority interrupt.
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*
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* Treat them like a true async interrupt.
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*/
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psignal(p, SIGFPE);
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}
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return (1);
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}
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/*
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* Wrapper for fnsave instruction to handle h/w bugs. If there is an error
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* pending, then fnsave generates a bogus IRQ13 on some systems. Force any
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* IRQ13 to be handled immediately, and then ignore it.
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*
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* This routine is always called at spl0. If it might called with the NPX
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* interrupt masked, it would be necessary to forcibly unmask the NPX interrupt
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* so that it could succeed.
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*
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* The FNSAVE instruction clears the FPU state. Rather than reloading the FPU
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* immediately, we clear npxproc and turn on CR0_TS to force a DNA and a reload
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* of the FPU state the next time we try to use it. Since this routine is only
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* called when forking, so this algorithm at worst forces us to trap once per
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* fork(), and at best saves us a reload once per fork().
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*/
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static inline void
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npxsave1()
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{
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register struct pcb *pcb;
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clts();
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npx_nointr = 1;
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pcb = &npxproc->p_addr->u_pcb;
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fnsave(&pcb->pcb_savefpu);
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pcb->pcb_cr0 |= CR0_TS;
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fwait();
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npx_nointr = 0;
|
|
}
|
|
|
|
/*
|
|
* Implement device not available (DNA) exception
|
|
*
|
|
* If the we were the last process to use the FPU, we can simply return.
|
|
* Otherwise, we save the previous state, if necessary, and restore our last
|
|
* saved state.
|
|
*/
|
|
int
|
|
npxdna()
|
|
{
|
|
register struct pcb *pcb = &curproc->p_addr->u_pcb;
|
|
|
|
if ((pcb->pcb_cr0 & CR0_EM) != 0) {
|
|
if (npx_type != NPX_NONE) {
|
|
iprintf(("Init"));
|
|
lcr0(pcb->pcb_cr0 &= ~CR0_EM);
|
|
npxinit();
|
|
return (1);
|
|
}
|
|
iprintf(("Emul"));
|
|
return (0);
|
|
}
|
|
|
|
#ifdef DIAGNOSTIC
|
|
if (cpl != 0 || npx_nointr != 0)
|
|
panic("npxdna: masked");
|
|
#endif
|
|
if (npxproc != 0) {
|
|
#ifdef DIAGNOSTIC
|
|
if (npxproc == curproc)
|
|
panic("npxdna: same process");
|
|
#endif
|
|
iprintf(("Save"));
|
|
npxsave1();
|
|
} else
|
|
clts();
|
|
/*
|
|
* The following frstor may cause an IRQ13 when the state being
|
|
* restored has a pending error. The error will appear to have been
|
|
* triggered by the current (npx) user instruction even when that
|
|
* instruction is a no-wait instruction that should not trigger an
|
|
* error (e.g., fnclex). On at least one 486 system all of the
|
|
* no-wait instructions are broken the same as frstor, so our
|
|
* treatment does not amplify the breakage. On at least one
|
|
* 386/Cyrix 387 system, fnclex works correctly while frstor and
|
|
* fnsave are broken, so our treatment breaks fnclex if it is the
|
|
* first FPU instruction after a context switch.
|
|
*/
|
|
pcb->pcb_cr0 &= ~CR0_TS;
|
|
npxproc = curproc;
|
|
frstor(&pcb->pcb_savefpu);
|
|
return (1);
|
|
}
|
|
|
|
void
|
|
npxsave()
|
|
{
|
|
|
|
#ifdef DIAGNOSTIC
|
|
if (cpl != 0 || npx_nointr != 0)
|
|
panic("npxsave: masked");
|
|
#endif
|
|
iprintf(("Fork"));
|
|
npxsave1();
|
|
if (npxproc == curproc)
|
|
stts();
|
|
npxproc = 0;
|
|
}
|
|
|
|
/*
|
|
* Initialize floating point unit.
|
|
*
|
|
* This is normally called at spl0, so NPX interrupts will be caught and
|
|
* ignored. It is called once during boot at splhigh, but there is never any
|
|
* state to save then.
|
|
*/
|
|
void
|
|
npxinit()
|
|
{
|
|
register struct pcb *pcb = &curproc->p_addr->u_pcb;
|
|
static u_short control = __INITIAL_NPXCW__;
|
|
#ifdef DIAGNOSTIC
|
|
extern int cold;
|
|
|
|
if (cpl != 0 && !cold || npx_nointr != 0)
|
|
panic("npxinit: masked");
|
|
#endif
|
|
if (npxproc != 0 && npxproc != curproc)
|
|
npxsave1();
|
|
else {
|
|
clts();
|
|
npx_nointr = 1;
|
|
fninit();
|
|
fwait();
|
|
npx_nointr = 0;
|
|
}
|
|
pcb->pcb_cr0 &= ~CR0_TS;
|
|
npxproc = curproc;
|
|
fldcw(&control);
|
|
}
|