53 lines
1.9 KiB
C
53 lines
1.9 KiB
C
/* $NetBSD: dp83905reg.h,v 1.1 2001/12/14 10:16:03 bjh21 Exp $ */
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/*
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* Ben Harris, 2001
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*
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* This file is in the public domain.
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*/
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/* dp83905reg.h - NatSemi DP83905 registers */
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/*
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* This file describes the special registers in the National
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* Semiconductor DP83905 AT/LANTIC AT Local Area Network Twisted-Pair
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* Interface Controller. The Macronix MX98905 is a clone of this chip.
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*
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* The DP83905 is a DP8390 with added glue logic to enable it to
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* emulate both an NE2000 and a WD 8319. It and its clones are
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* commonly used on podulebus Ethernet cards.
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*/
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/* Extra registers (in page 0) */
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#define DP83905_MCRA 0x0a
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#define DP83905_MCRB 0x0b
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#define DP83905_MCRA_IOADDR_MASK 0x07 /* I/O Address */
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#define DP83905_MCRA_IOADDR_300 0x00
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#define DP83905_MCRA_IOADDR_SOFT 0x01
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#define DP83905_MCRA_IOADDR_240 0x02
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#define DP83905_MCRA_IOADDR_280 0x03
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#define DP83905_MCRA_IOADDR_2C0 0x04
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#define DP83905_MCRA_IOADDR_320 0x05
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#define DP83905_MCRA_IOADDR_340 0x06
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#define DP83905_MCRA_IOADDR_360 0x07
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#define DP83905_MCRA_INT_MASK 0x38 /* Interrupt line used */
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#define DP83905_MCRA_INT0 0x00
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#define DP83905_MCRA_INT1 0x08
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#define DP83905_MCRA_INT2 0x10
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#define DP83905_MCRA_INT3 0x18
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#define DP83905_MCRA_FREAD 0x40 /* Fast read */
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#define DP83905_MCRA_MEMIO 0x80 /* Memory or I/O mode (1=>mem) */
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#define DP83905_MCRB_PHY_MASK 0x03 /* Physical layer interface */
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#define DP83905_MCRB_PHY_10_T 0x00 /* TPI (10BASE-T squelch) */
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#define DP83905_MCRB_PHY_10_2 0x01 /* Thin Ethernet (10BASE2) */
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#define DP83905_MCRB_PHY_AUI 0x02 /* Thick Ethernet (10BASE5/AUI) */
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#define DP83905_MCRB_PHY_TPI_NONSPEC 0x03 /* TPI (Reduced squelch) */
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#define DP83905_MCRB_GDLNK 0x04 /* Good link */
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#define DP83905_MCRB_IO16CON 0x08 /* IO16* control */
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#define DP83905_MCRB_CHRDY 0x10 /* CHRDY from IORD/WR* or BALE */
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#define DP83905_MCRB_BE 0x20 /* Bus error */
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#define DP83905_MCRB_BPWR 0x40 /* Boot PROM write */
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#define DP83905_MCRB_EELOAD 0x80 /* EEPROM load */
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