62 lines
2.3 KiB
C
62 lines
2.3 KiB
C
/* $NetBSD: fpureg.h,v 1.1 2002/03/24 15:46:58 bjh21 Exp $ */
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/*
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* ARM FPU definitions
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*/
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/* System ID byte */
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#define FPSR_SYSID_MASK 0xff000000
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#define FPSR_SYSID_FPPC 0x80000000
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#define FPSR_SYSID_FPA 0x81000000
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/* Trap enable bits */
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#define FPSR_TE_IVO 0x00010000 /* InValid Operation */
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#define FPSR_TE_DVZ 0x00020000 /* DiVision by Zero */
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#define FPSR_TE_OFL 0x00040000 /* OverFLow */
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#define FPSR_TE_UFL 0x00080000 /* UnderFLow */
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#define FPSR_TE_INX 0x00100000 /* INeXact */
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/* System control byte (FPA only) */
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#define FPSR_CTL_ND 0x00000100 /* No Denormalised numbers */
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#define FPSR_CTL_NE 0x00000200 /* NaN Exception */
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#define FPSR_CTL_SO 0x00000400 /* Synchronous Operation */
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#define FPSR_CTL_EP 0x00000800 /* Expanded Packed decimal */
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#define FPSR_CTL_AC 0x00001000 /* Alternative C flag */
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/* Cumulative exception bits */
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#define FPSR_EX_IVO 0x00000001 /* InValid Operation */
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#define FPSR_EX_DVZ 0x00000002 /* DiVision by Zero */
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#define FPSR_EX_OFL 0x00000004 /* OverFLow */
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#define FPSR_EX_UFL 0x00000008 /* UnderFLow */
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#define FPSR_EX_INX 0x00000010 /* INeXact */
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/*
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* FPPC FPCR
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*/
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#define FPPC_FPCR_DA 0x00000001 /* Disable */
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#define FPPC_FPCR_EX 0x00000002 /* FP exception occurred */
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#define FPPC_FPCR_AS 0x00000004 /* Last exception was async */
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#define FPPC_FPCR_SBM 0x00000010 /* Use supervisor bank 'm' */
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#define FPPC_FPCR_SBN 0x00000020 /* Use supervisor bank 'n' */
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#define FPPC_FPCR_SBD 0x00000040 /* Use supervisor bank 'd' */
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#define FPPC_FPCR_PR 0x00000080 /* Last RMF gave partial remainder */
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/*
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* FPA FPCR
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* This is provisional, from the RISC OS 3 PRM
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*/
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#define FPA_FPCR_S2 0x0000000f /* AU source register 2 */
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#define FPA_FPCR_OP 0x00f08010 /* AU operation code */
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#define FPA_FPCR_RM 0x00000060 /* AU rounding mode */
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#define FPA_FPCR_PR 0x00080080 /* AU precision */
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#define FPA_FPCR_EN 0x00000100 /* Enable FPA */
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#define FPA_FPCR_RE 0x00000200 /* Rounding exception */
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#define FPA_FPCR_AB 0x00000400 /* Asynchronous bounce */
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#define FPA_FPCR_SB 0x00000800 /* Synchronous bounce */
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#define FPA_FPCR_DS 0x00007000 /* AU destination register */
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#define FPA_FPCR_S1 0x00070000 /* AU source register 1 */
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#define FPA_FPCR_EO 0x04000000 /* Exponent overflow */
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#define FPA_FPCR_MO 0x08000000 /* Mantissa overflow */
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#define FPA_FPCR_IE 0x10000000 /* Inexact bit */
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#define FPA_FPCR_RU 0x80000000 /* Rounded up bit */
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