369 lines
13 KiB
C
369 lines
13 KiB
C
/* $NetBSD: i82557var.h,v 1.31 2003/05/26 16:14:49 yamt Exp $ */
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/*-
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* Copyright (c) 1997, 1998, 1999, 2001 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
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* NASA Ames Research Center.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the NetBSD
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* Foundation, Inc. and its contributors.
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* 4. Neither the name of The NetBSD Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Copyright (c) 1995, David Greenman
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice unmodified, this list of conditions, and the following
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* disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* Id: if_fxpvar.h,v 1.4 1997/11/29 08:11:01 davidg Exp
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*/
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#include <sys/callout.h>
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/*
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* Misc. definitions for the Intel i82557 fast Ethernet controller
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* driver.
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*/
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/*
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* Transmit descriptor list size.
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*/
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#define FXP_NTXCB 256
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#define FXP_NTXCB_MASK (FXP_NTXCB - 1)
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#define FXP_NEXTTX(x) ((x + 1) & FXP_NTXCB_MASK)
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#define FXP_NTXSEG 16
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#define FXP_IPCB_NTXSEG (FXP_NTXSEG - 1)
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/*
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* Number of receive frame area buffers. These are large, so
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* choose wisely.
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*/
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#define FXP_NRFABUFS 128
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/*
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* Maximum number of seconds that the receiver can be idle before we
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* assume it's dead and attempt to reset it by reprogramming the
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* multicast filter. This is part of a work-around for a bug in the
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* NIC. See fxp_stats_update().
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*/
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#define FXP_MAX_RX_IDLE 15
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/*
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* Misc. DMA'd data structures are allocated in a single clump, that
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* maps to a single DMA segment, to make several things easier (computing
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* offsets, setting up DMA maps, etc.)
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*/
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struct fxp_control_data {
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/*
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* The transmit control blocks and transmit buffer descriptors.
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* We arrange them like this so that everything is all lined
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* up to use the extended TxCB feature.
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*/
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struct fxp_txdesc {
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struct fxp_cb_tx txd_txcb;
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union {
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struct fxp_ipcb txdu_ipcb;
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struct fxp_tbd txdu_tbd[FXP_NTXSEG];
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} txd_u;
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} fcd_txdescs[FXP_NTXCB];
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/*
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* The configuration CB.
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*/
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struct fxp_cb_config fcd_configcb;
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/*
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* The Individual Address CB.
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*/
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struct fxp_cb_ias fcd_iascb;
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/*
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* The multicast setup CB.
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*/
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struct fxp_cb_mcs fcd_mcscb;
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/*
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* The microcode setup CB.
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*/
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struct fxp_cb_ucode fcd_ucode;
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/*
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* The NIC statistics.
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*/
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struct fxp_stats fcd_stats;
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};
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#define txd_tbd txd_u.txdu_tbd
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#define FXP_CDOFF(x) offsetof(struct fxp_control_data, x)
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#define FXP_CDTXOFF(x) FXP_CDOFF(fcd_txdescs[(x)].txd_txcb)
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#define FXP_CDTBDOFF(x) FXP_CDOFF(fcd_txdescs[(x)].txd_tbd)
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#define FXP_CDCONFIGOFF FXP_CDOFF(fcd_configcb)
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#define FXP_CDIASOFF FXP_CDOFF(fcd_iascb)
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#define FXP_CDMCSOFF FXP_CDOFF(fcd_mcscb)
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#define FXP_CDUCODEOFF FXP_CDOFF(fcd_ucode)
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#define FXP_CDSTATSOFF FXP_CDOFF(fcd_stats)
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/*
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* Software state for transmit descriptors.
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*/
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struct fxp_txsoft {
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struct mbuf *txs_mbuf; /* head of mbuf chain */
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bus_dmamap_t txs_dmamap; /* our DMA map */
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};
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/*
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* Software state per device.
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*/
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struct fxp_softc {
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struct device sc_dev; /* generic device structures */
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bus_space_tag_t sc_st; /* bus space tag */
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bus_space_handle_t sc_sh; /* bus space handle */
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bus_dma_tag_t sc_dmat; /* bus dma tag */
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struct ethercom sc_ethercom; /* ethernet common part */
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void *sc_sdhook; /* shutdown hook */
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void *sc_ih; /* interrupt handler cookie */
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void *sc_powerhook; /* power hook */
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struct mii_data sc_mii; /* MII/media information */
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struct callout sc_callout; /* MII callout */
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/*
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* We create a single DMA map that maps all data structure
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* overhead, except for RFAs, which are mapped by the
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* fxp_rxdesc DMA map on a per-mbuf basis.
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*/
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bus_dmamap_t sc_dmamap;
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#define sc_cddma sc_dmamap->dm_segs[0].ds_addr
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/*
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* Software state for transmit descriptors.
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*/
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struct fxp_txsoft sc_txsoft[FXP_NTXCB];
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int sc_rfa_size; /* size of the RFA structure */
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struct ifqueue sc_rxq; /* receive buffer queue */
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bus_dmamap_t sc_rxmaps[FXP_NRFABUFS]; /* free receive buffer DMA maps */
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int sc_rxfree; /* free map index */
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int sc_rxidle; /* # of seconds RX has been idle */
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u_int16_t sc_txcmd; /* transmit command (LITTLE ENDIAN) */
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/*
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* Control data structures.
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*/
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struct fxp_control_data *sc_control_data;
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#ifdef FXP_EVENT_COUNTERS
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struct evcnt sc_ev_txstall; /* Tx stalled */
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struct evcnt sc_ev_txintr; /* Tx interrupts */
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struct evcnt sc_ev_rxintr; /* Rx interrupts */
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#endif /* FXP_EVENT_COUNTERS */
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bus_dma_segment_t sc_cdseg; /* control dma segment */
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int sc_cdnseg;
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int sc_rev; /* chip revision */
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int sc_flags; /* misc. flags */
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#define FXPF_MII 0x0001 /* device uses MII */
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#define FXPF_ATTACHED 0x0002 /* attach has succeeded */
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#define FXPF_WANTINIT 0x0004 /* want a re-init */
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#define FXPF_HAS_RESUME_BUG 0x0008 /* has the resume bug */
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#define FXPF_MWI 0x0010 /* enable PCI MWI */
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#define FXPF_READ_ALIGN 0x0020 /* align read access w/ cacheline */
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#define FXPF_WRITE_ALIGN 0x0040 /* end write on cacheline */
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#define FXPF_EXT_TXCB 0x0080 /* enable extended TxCB */
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#define FXPF_UCODE_LOADED 0x0100 /* microcode is loaded */
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#define FXPF_EXT_RFA 0x0200 /* enable extended RFD */
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#define FXPF_IPCB 0x0400 /* use IPCB */
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int sc_int_delay; /* interrupt delay */
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int sc_bundle_max; /* max packet bundle */
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int sc_txpending; /* number of TX requests pending */
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int sc_txdirty; /* first dirty TX descriptor */
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int sc_txlast; /* last used TX descriptor */
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int phy_primary_device; /* device type of primary PHY */
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int sc_enabled; /* boolean; power enabled on interface */
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int (*sc_enable)(struct fxp_softc *);
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void (*sc_disable)(struct fxp_softc *);
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int sc_eeprom_size; /* log2 size of EEPROM */
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#if NRND > 0
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rndsource_element_t rnd_source; /* random source */
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#endif
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};
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#ifdef FXP_EVENT_COUNTERS
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#define FXP_EVCNT_INCR(ev) (ev)->ev_count++
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#else
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#define FXP_EVCNT_INCR(ev) /* nothing */
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#endif
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#define FXP_RXMAP_GET(sc) ((sc)->sc_rxmaps[(sc)->sc_rxfree++])
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#define FXP_RXMAP_PUT(sc, map) (sc)->sc_rxmaps[--(sc)->sc_rxfree] = (map)
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#define FXP_CDTXADDR(sc, x) ((sc)->sc_cddma + FXP_CDTXOFF((x)))
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#define FXP_CDTBDADDR(sc, x) ((sc)->sc_cddma + FXP_CDTBDOFF((x)))
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#define FXP_CDTX(sc, x) (&(sc)->sc_control_data->fcd_txdescs[(x)])
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#define FXP_DSTX(sc, x) (&(sc)->sc_txsoft[(x)])
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#define FXP_CDTXSYNC(sc, x, ops) \
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bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_dmamap, \
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FXP_CDTXOFF((x)), sizeof(struct fxp_txdesc), (ops))
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#define FXP_CDCONFIGSYNC(sc, ops) \
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bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_dmamap, \
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FXP_CDCONFIGOFF, sizeof(struct fxp_cb_config), (ops))
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#define FXP_CDIASSYNC(sc, ops) \
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bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_dmamap, \
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FXP_CDIASOFF, sizeof(struct fxp_cb_ias), (ops))
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#define FXP_CDMCSSYNC(sc, ops) \
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bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_dmamap, \
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FXP_CDMCSOFF, sizeof(struct fxp_cb_mcs), (ops))
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#define FXP_CDUCODESYNC(sc, ops) \
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bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_dmamap, \
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FXP_CDUCODEOFF, sizeof(struct fxp_cb_ucode), (ops))
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#define FXP_CDSTATSSYNC(sc, ops) \
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bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_dmamap, \
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FXP_CDSTATSOFF, sizeof(struct fxp_stats), (ops))
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#define FXP_RXBUFSIZE(sc, m) ((m)->m_ext.ext_size - \
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(sc->sc_rfa_size + \
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RFA_ALIGNMENT_FUDGE))
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#define FXP_RFASYNC(sc, m, ops) \
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bus_dmamap_sync((sc)->sc_dmat, M_GETCTX((m), bus_dmamap_t), \
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RFA_ALIGNMENT_FUDGE, (sc)->sc_rfa_size, (ops))
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#define FXP_RXBUFSYNC(sc, m, ops) \
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bus_dmamap_sync((sc)->sc_dmat, M_GETCTX((m), bus_dmamap_t), \
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RFA_ALIGNMENT_FUDGE + (sc)->sc_rfa_size, \
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FXP_RXBUFSIZE((sc), (m)), (ops))
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#define FXP_MTORFA(m) (struct fxp_rfa *)((m)->m_ext.ext_buf + \
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RFA_ALIGNMENT_FUDGE)
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#define FXP_INIT_RFABUF(sc, m) \
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do { \
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bus_dmamap_t __rxmap = M_GETCTX((m), bus_dmamap_t); \
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struct mbuf *__p_m; \
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struct fxp_rfa *__rfa, *__p_rfa; \
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u_int32_t __v; \
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\
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(m)->m_data = (m)->m_ext.ext_buf + (sc)->sc_rfa_size + \
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RFA_ALIGNMENT_FUDGE; \
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\
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__rfa = FXP_MTORFA((m)); \
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__rfa->size = htole16(FXP_RXBUFSIZE((sc), (m))); \
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/* BIG_ENDIAN: no need to swap to store 0 */ \
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__rfa->rfa_status = 0; \
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__rfa->rfa_control = htole16(FXP_RFA_CONTROL_EL); \
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/* BIG_ENDIAN: no need to swap to store 0 */ \
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__rfa->actual_size = 0; \
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\
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/* NOTE: the RFA is misaligned, so we must copy. */ \
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/* BIG_ENDIAN: no need to swap to store 0xffffffff */ \
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__v = 0xffffffff; \
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memcpy((void *)&__rfa->link_addr, &__v, sizeof(__v)); \
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memcpy((void *)&__rfa->rbd_addr, &__v, sizeof(__v)); \
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\
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FXP_RFASYNC((sc), (m), \
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BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \
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\
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FXP_RXBUFSYNC((sc), (m), BUS_DMASYNC_PREREAD); \
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\
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if ((__p_m = (sc)->sc_rxq.ifq_tail) != NULL) { \
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__p_rfa = FXP_MTORFA(__p_m); \
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__v = htole32(__rxmap->dm_segs[0].ds_addr + \
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RFA_ALIGNMENT_FUDGE); \
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FXP_RFASYNC((sc), __p_m, \
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BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); \
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memcpy((void *)&__p_rfa->link_addr, &__v, \
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sizeof(__v)); \
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__p_rfa->rfa_control &= htole16(~FXP_RFA_CONTROL_EL); \
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FXP_RFASYNC((sc), __p_m, \
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BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \
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} \
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IF_ENQUEUE(&(sc)->sc_rxq, (m)); \
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} while (0)
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/* Macros to ease CSR access. */
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#define CSR_READ_1(sc, reg) \
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bus_space_read_1((sc)->sc_st, (sc)->sc_sh, (reg))
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#define CSR_READ_2(sc, reg) \
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bus_space_read_2((sc)->sc_st, (sc)->sc_sh, (reg))
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#define CSR_READ_4(sc, reg) \
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bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg))
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#define CSR_WRITE_1(sc, reg, val) \
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bus_space_write_1((sc)->sc_st, (sc)->sc_sh, (reg), (val))
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#define CSR_WRITE_2(sc, reg, val) \
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bus_space_write_2((sc)->sc_st, (sc)->sc_sh, (reg), (val))
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#define CSR_WRITE_4(sc, reg, val) \
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bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val))
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void fxp_attach(struct fxp_softc *);
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int fxp_activate(struct device *, enum devact);
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int fxp_detach(struct fxp_softc *);
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int fxp_intr(void *);
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int fxp_enable(struct fxp_softc*);
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void fxp_disable(struct fxp_softc*);
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