154 lines
6.2 KiB
C
154 lines
6.2 KiB
C
/* $NetBSD: mmu_sh4.h,v 1.2 2002/02/28 01:56:58 uch Exp $ */
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/*-
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* Copyright (c) 2002 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by UCHIYAMA Yasushi.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the NetBSD
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* Foundation, Inc. and its contributors.
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* 4. Neither the name of The NetBSD Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _SH3_MMU_SH4_H_
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#define _SH3_MMU_SH4_H_
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#include <sh3/devreg.h>
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/* ITLB 4-entry full-associative UTLB 64-entry full-associative */
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#define SH4_PTEH 0xff000000
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#define SH4_PTEH_VPN_MASK 0xfffffc00
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#define SH4_PTEH_ASID_MASK 0x0000000f
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#define SH4_PTEL 0xff000004
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#define SH4_PTEL_WT 0x00000001
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#define SH4_PTEL_SH 0x00000002
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#define SH4_PTEL_D 0x00000004
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#define SH4_PTEL_C 0x00000008
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#define SH4_PTEL_PR_SHIFT 5
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#define SH4_PTEL_PR_MASK 0x00000060 /* [5:6] */
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#define SH4_PTEL_SZ_MASK 0x00000090 /* [4][7] */
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#define SH4_PTEL_SZ_1K 0x00000000
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#define SH4_PTEL_SZ_4K 0x00000010
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#define SH4_PTEL_SZ_64K 0x00000080
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#define SH4_PTEL_SZ_1M 0x00000090
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#define SH4_PTEL_V 0x00000100
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#define SH4_PTEL_HWBITS 0x1ffff1ff /* [28:12]PFN [8:0]attr. */
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#define SH4_PTEA 0xff000034
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#define SH4_PTEA_SA_MASK 0x00000007
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#define SH4_PTEA_SA_TC 0x00000008
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#define SH4_TTB 0xff000008
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#define SH4_TEA 0xff00000c
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#define SH4_MMUCR 0xff000010
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#define SH4_MMUCR_AT 0x00000001
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#define SH4_MMUCR_TI 0x00000004
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#define SH4_MMUCR_SV 0x00000100
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#define SH4_MMUCR_SQMD 0x00000200
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#define SH4_MMUCR_URC_SHIFT 10
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#define SH4_MMUCR_URC_MASK 0x0000fc00 /* [10:15] */
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#define SH4_MMUCR_URB_SHIFT 18
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#define SH4_MMUCR_URB_MASK 0x00fc0000 /* [18:23] */
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#define SH4_MMUCR_LRUI_SHIFT 26
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#define SH4_MMUCR_LRUT_MASK 0xfc000000 /* [26:31] */
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#define SH4_MMUCR_MASK (SH4_MMUCR_LRUT_MASK | SH4_MMUCR_URB_MASK | \
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SH4_MMUCR_URC_MASK | SH4_MMUCR_SQMD | SH4_MMUCR_SV | SH4_MMUCR_AT)
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/*
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* memory-mapped TLB
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* must be access from P2-area program.
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* branch to the other area must be maed at least 8 instruction
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* after access.
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*/
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#define SH4_ITLB_ENTRY 4
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#define SH4_UTLB_ENTRY 64
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/* ITLB */
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#define SH4_ITLB_AA 0xf2000000
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/* address specification (common for address and data array(0,1)) */
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#define SH4_ITLB_E_SHIFT 8
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#define SH4_ITLB_E_MASK 0x00000300 /* [9:8] */
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/* data specification */
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/* address-array */
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#define SH4_ITLB_AA_ASID_MASK 0x000000ff /* [7:0] */
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#define SH4_ITLB_AA_V 0x00000100
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#define SH4_ITLB_AA_VPN_SHIFT 10
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#define SH4_ITLB_AA_VPN_MASK 0xfffffc00 /* [31:10] */
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/* data-array 1 */
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#define SH4_ITLB_DA1 0xf3000000
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#define SH4_ITLB_DA1_SH 0x00000002
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#define SH4_ITLB_DA1_C 0x00000008
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#define SH4_ITLB_DA1_SZ_MASK 0x00000090 /* [7][4] */
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#define SH4_ITLB_DA1_SZ_1K 0x00000000
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#define SH4_ITLB_DA1_SZ_4K 0x00000010
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#define SH4_ITLB_DA1_SZ_64K 0x00000080
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#define SH4_ITLB_DA1_SZ_1M 0x00000090
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#define SH4_ITLB_DA1_PR 0x00000040
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#define SH4_ITLB_DA1_V 0x00000100
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#define SH4_ITLB_DA1_PPN_SHIFT 11
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#define SH4_ITLB_DA1_PPN_MASK 0x1ffffc00 /* [28:10] */
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/* data-array 2 */
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#define SH4_ITLB_DA2 0xf3800000
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#define SH4_ITLB_DA2_SA_MASK 0x00000003
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#define SH4_ITLB_DA2_TC 0x00000004
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/* UTLB */
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#define SH4_UTLB_AA 0xf6000000
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/* address specification (common for address and data array(0,1)) */
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#define SH4_UTLB_E_SHIFT 8
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#define SH4_UTLB_E_MASK 0x00003f00
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#define SH4_UTLB_A 0x00000080
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/* data specification */
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/* address-array */
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#define SH4_UTLB_AA_VPN_MASK 0xfffffc00 /* [31:10] */
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#define SH4_UTLB_AA_D 0x00000200
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#define SH4_UTLB_AA_V 0x00000100
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#define SH4_UTLB_AA_ASID_MASK 0x000000ff /* [7:0] */
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/* data-array 1 */
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#define SH4_UTLB_DA1 0xf7000000
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#define SH4_UTLB_DA1_WT 0x00000001
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#define SH4_UTLB_DA1_SH 0x00000002
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#define SH4_UTLB_DA1_D 0x00000004
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#define SH4_UTLB_DA1_C 0x00000008
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#define SH4_UTLB_DA1_SZ_MASK 0x00000090 /* [7][4] */
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#define SH4_UTLB_DA1_SZ_1K 0x00000000
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#define SH4_UTLB_DA1_SZ_4K 0x00000010
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#define SH4_UTLB_DA1_SZ_64K 0x00000080
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#define SH4_UTLB_DA1_SZ_1M 0x00000090
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#define SH4_UTLB_DA1_PR_SHIFT 5
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#define SH4_UTLB_DA1_PR_MASK 0x00000060
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#define SH4_UTLB_DA1_V 0x00000100
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#define SH4_UTLB_DA1_PPN_SHIFT 11
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#define SH4_UTLB_DA1_PPN_MASK 0x1ffffc00 /* [28:10] */
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/* data-array 2 */
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#define SH4_UTLB_DA2 0xf7800000
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#define SH4_UTLB_DA2_SA_MASK 0x00000003
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#define SH4_UTLB_DA2_TC 0x00000004
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#define SH4_TLB_DISABLE *(__volatile__ u_int32_t *)SH4_MMUCR = SH4_MMUCR_TI
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#endif /* !_SH3_MMU_SH4_H_ */
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