dd0e0396bc
XXX It's experimental code yet. For x68k: USB part of Nereid USB/Ethernet/memory board For ISA: ISA USB Host board from Morphy planning
125 lines
5.2 KiB
C
125 lines
5.2 KiB
C
/* $NetBSD: sl811hsreg.h,v 1.1 2002/08/11 13:17:53 isaki Exp $ */
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/*
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* Copyright (c) 2001 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Tetsuya Isaki.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the NetBSD
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* Foundation, Inc. and its contributors.
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* 4. Neither the name of The NetBSD Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* ScanLogic SL811HS/T USB Host Controller
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*/
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#define SL11_IDX_ADDR (0x00)
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#define SL11_IDX_DATA (0x01)
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#define SL11_PORTSIZE (0x02)
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#define SL11_E0BASE (0x00) /* Base of Control0 */
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#define SL11_E0CTRL (0x00) /* Host Control Register */
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#define SL11_E0ADDR (0x01) /* Host Base Address */
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#define SL11_E0LEN (0x02) /* Host Base Length */
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#define SL11_E0STAT (0x03) /* USB Status (Read) */
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#define SL11_E0PID SL11_E0STAT /* Host PID, Device Endpoint (Write) */
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#define SL11_E0CONT (0x04) /* Transfer Count (Read) */
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#define SL11_E0DEV SL11_E0CONT /* Host Device Address (Write) */
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#define SL11_E1BASE (0x08) /* Base of Control1 */
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#define SL11_E1CTRL (SL11_E1BASE + SL11_E0CTRL)
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#define SL11_E1ADDR (SL11_E1BASE + SL11_E0ADDR)
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#define SL11_E1LEN (SL11_E1BASE + SL11_E0LEN)
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#define SL11_E1STAT (SL11_E1BASE + SL11_E0STAT)
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#define SL11_E1PID (SL11_E1BASE + SL11_E0PID)
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#define SL11_E1CONT (SL11_E1BASE + SL11_E0CONT)
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#define SL11_E1DEV (SL11_E1BASE + SL11_E0DEV)
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#define SL11_CTRL (0x05) /* Control Register1 */
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#define SL11_IER (0x06) /* Interrupt Enable Register */
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#define SL11_ISR (0x0d) /* Interrupt Status Register */
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#define SL11_DATA (0x0e) /* SOF Counter Low (Write) */
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#define SL11_REV SL11_DATA /* HW Revision Register (Read) */
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#define SL811_CSOF (0x0f) /* SOF Counter High(R), Control2(W) */
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#define SL11_MEM (0x10) /* Memory Buffer (0x10 - 0xff) */
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#define SL11_EPCTRL_ARM (0x01)
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#define SL11_EPCTRL_ENABLE (0x02)
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#define SL11_EPCTRL_DIRECTION (0x04)
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#define SL11_EPCTRL_ISO (0x10)
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#define SL11_EPCTRL_SOF (0x20)
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#define SL11_EPCTRL_DATATOGGLE (0x40)
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#define SL11_EPCTRL_PREAMBLE (0x80)
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#define SL11_EPPID_PIDMASK (0xf0)
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#define SL11_EPPID_EPMASK (0x0f)
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#define SL11_EPSTAT_ACK (0x01)
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#define SL11_EPSTAT_ERROR (0x02)
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#define SL11_EPSTAT_TIMEOUT (0x04)
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#define SL11_EPSTAT_SEQUENCE (0x08)
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#define SL11_EPSTAT_SETUP (0x10)
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#define SL11_EPSTAT_OVERFLOW (0x20)
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#define SL11_EPSTAT_NAK (0x40)
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#define SL11_EPSTAT_STALL (0x80)
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#define SL11_CTRL_ENABLESOF (0x01)
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#define SL11_CTRL_EOF2 (0x04)
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#define SL11_CTRL_RESETENGINE (0x08)
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#define SL11_CTRL_JKSTATE (0x10)
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#define SL11_CTRL_LOWSPEED (0x20)
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#define SL11_CTRL_SUSPEND (0x40)
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#define SL11_IER_USBA (0x01) /* USB-A done */
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#define SL11_IER_USBB (0x02) /* USB-B done */
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#define SL11_IER_BABBLE (0x04) /* Babble detection */
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#define SL11_IER_SOFTIMER (0x10) /* 1ms SOF timer */
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#define SL11_IER_INSERT (0x20) /* Slave Insert/Remove detection */
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#define SL11_IER_RESET (0x40) /* USB Reset/Resume */
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#define SL11_ISR_USBA (0x01) /* USB-A done */
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#define SL11_ISR_USBB (0x02) /* USB-B done */
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#define SL11_ISR_BABBLE (0x04) /* Babble detection */
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#define SL11_ISR_SOFTIMER (0x10) /* 1ms SOF timer */
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#define SL11_ISR_INSERT (0x20) /* Slave Insert/Remove detection */
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#define SL11_ISR_RESET (0x40) /* USB Reset/Resume */
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#define SL11_ISR_DATA (0x80) /* Value of the Data+ pin */
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#define SL11_REV_USBA (0x01) /* USB-A */
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#define SL11_REV_USBB (0x02) /* USB-B */
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#define SL11_REV_REVMASK (0xf0) /* HW Revision */
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#define SL11_REV_REVSL11H (0x00) /* HW is SL11H */
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#define SL11_REV_REVSL811HS (0x10) /* HW is SL811HS */
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#define SL811_CSOF_SOFMASK (0x3f) /* SOF High Counter */
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#define SL811_CSOF_POLARITY (0x40) /* Change polarity */
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#define SL811_CSOF_MASTER (0x80) /* Master/Slave selection */
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