7dd7f8baa2
enabled on amd64). Add a dmat64 field to various PCI attach structures, and pass it down where needed. Implement a simple new function called pci_dma64_available(pa) to test if 64bit DMA addresses may be used. This returns 1 iff _PCI_HAVE_DMA64 is defined in <machine/pci_machdep.h>, and there is more than 4G of memory.
595 lines
21 KiB
C
595 lines
21 KiB
C
/* $NetBSD: bus.h,v 1.8 2003/06/15 23:08:58 fvdl Exp $ */
|
|
|
|
/*-
|
|
* Copyright (c) 1997, 1998, 2000, 2001 The NetBSD Foundation, Inc.
|
|
* All rights reserved.
|
|
*
|
|
* This code is derived from software contributed to The NetBSD Foundation
|
|
* by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
|
|
* NASA Ames Research Center.
|
|
*
|
|
* Redistribution and use in source and binary forms, with or without
|
|
* modification, are permitted provided that the following conditions
|
|
* are met:
|
|
* 1. Redistributions of source code must retain the above copyright
|
|
* notice, this list of conditions and the following disclaimer.
|
|
* 2. Redistributions in binary form must reproduce the above copyright
|
|
* notice, this list of conditions and the following disclaimer in the
|
|
* documentation and/or other materials provided with the distribution.
|
|
* 3. All advertising materials mentioning features or use of this software
|
|
* must display the following acknowledgement:
|
|
* This product includes software developed by the NetBSD
|
|
* Foundation, Inc. and its contributors.
|
|
* 4. Neither the name of The NetBSD Foundation nor the names of its
|
|
* contributors may be used to endorse or promote products derived
|
|
* from this software without specific prior written permission.
|
|
*
|
|
* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
|
|
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
|
|
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
|
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
|
|
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
|
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
|
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
|
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
|
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
|
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
|
* POSSIBILITY OF SUCH DAMAGE.
|
|
*/
|
|
|
|
/*
|
|
* Copyright (c) 1996 Carnegie-Mellon University.
|
|
* All rights reserved.
|
|
*
|
|
* Author: Chris G. Demetriou
|
|
*
|
|
* Permission to use, copy, modify and distribute this software and
|
|
* its documentation is hereby granted, provided that both the copyright
|
|
* notice and this permission notice appear in all copies of the
|
|
* software, derivative works or modified versions, and any portions
|
|
* thereof, and that both notices appear in supporting documentation.
|
|
*
|
|
* CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
|
|
* CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
|
|
* FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
|
|
*
|
|
* Carnegie Mellon requests users of this software to return to
|
|
*
|
|
* Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
|
|
* School of Computer Science
|
|
* Carnegie Mellon University
|
|
* Pittsburgh PA 15213-3890
|
|
*
|
|
* any improvements or extensions that they make and grant Carnegie the
|
|
* rights to redistribute these changes.
|
|
*/
|
|
|
|
#ifndef _DREAMCAST_BUS_H_
|
|
#define _DREAMCAST_BUS_H_
|
|
|
|
#include <sys/types.h>
|
|
|
|
#ifdef _KERNEL
|
|
/*
|
|
* Turn on BUS_SPACE_DEBUG if the global DEBUG option is enabled.
|
|
*/
|
|
#if defined(DEBUG) && !defined(BUS_SPACE_DEBUG)
|
|
#define BUS_SPACE_DEBUG
|
|
#endif
|
|
|
|
#ifdef BUS_SPACE_DEBUG
|
|
#include <sys/systm.h> /* for printf() prototype */
|
|
/*
|
|
* Macros for checking the aligned-ness of pointers passed to bus
|
|
* space ops. Strict alignment is required by the Alpha architecture,
|
|
* and a trap will occur if unaligned access is performed. These
|
|
* may aid in the debugging of a broken device driver by displaying
|
|
* useful information about the problem.
|
|
*/
|
|
#define __BUS_SPACE_ALIGNED_ADDRESS(p, t) \
|
|
((((u_long)(p)) & (sizeof(t)-1)) == 0)
|
|
|
|
#define __BUS_SPACE_ADDRESS_SANITY(p, t, d) \
|
|
({ \
|
|
if (__BUS_SPACE_ALIGNED_ADDRESS((p), t) == 0) { \
|
|
printf("%s 0x%lx not aligned to %lu bytes %s:%d\n", \
|
|
d, (u_long)(p), (u_long)sizeof(t), __FILE__, __LINE__); \
|
|
} \
|
|
(void) 0; \
|
|
})
|
|
|
|
#define BUS_SPACE_ALIGNED_POINTER(p, t) __BUS_SPACE_ALIGNED_ADDRESS(p, t)
|
|
#else
|
|
#define __BUS_SPACE_ADDRESS_SANITY(p, t, d) (void) 0
|
|
#define BUS_SPACE_ALIGNED_POINTER(p, t) ALIGNED_POINTER(p, t)
|
|
#endif /* BUS_SPACE_DEBUG */
|
|
#endif /* _KERNEL */
|
|
|
|
/*
|
|
* Addresses (in bus space).
|
|
*/
|
|
typedef u_long bus_addr_t;
|
|
typedef u_long bus_size_t;
|
|
|
|
/*
|
|
* Access methods for bus space.
|
|
*/
|
|
typedef struct dreamcast_bus_space *bus_space_tag_t;
|
|
typedef u_long bus_space_handle_t;
|
|
|
|
struct dreamcast_bus_space {
|
|
/* cookie */
|
|
void *dbs_cookie;
|
|
|
|
/* mapping/unmapping */
|
|
int (*dbs_map)(void *, bus_addr_t, bus_size_t,
|
|
int, bus_space_handle_t *);
|
|
void (*dbs_unmap)(void *, bus_space_handle_t,
|
|
bus_size_t);
|
|
int (*dbs_subregion)(void *, bus_space_handle_t,
|
|
bus_size_t, bus_size_t, bus_space_handle_t *);
|
|
|
|
/* allocation/deallocation */
|
|
int (*dbs_alloc)(void *, bus_addr_t, bus_addr_t,
|
|
bus_size_t, bus_size_t, bus_size_t, int,
|
|
bus_addr_t *, bus_space_handle_t *);
|
|
void (*dbs_free)(void *, bus_space_handle_t,
|
|
bus_size_t);
|
|
|
|
/* get kernel virtual address */
|
|
void * (*dbs_vaddr)(void *, bus_space_handle_t);
|
|
|
|
/* read (single) */
|
|
u_int8_t (*dbs_r_1)(void *, bus_space_handle_t,
|
|
bus_size_t);
|
|
u_int16_t (*dbs_r_2)(void *, bus_space_handle_t,
|
|
bus_size_t);
|
|
u_int32_t (*dbs_r_4)(void *, bus_space_handle_t,
|
|
bus_size_t);
|
|
u_int64_t (*dbs_r_8)(void *, bus_space_handle_t,
|
|
bus_size_t);
|
|
|
|
/* read multiple */
|
|
void (*dbs_rm_1)(void *, bus_space_handle_t,
|
|
bus_size_t, u_int8_t *, bus_size_t);
|
|
void (*dbs_rm_2)(void *, bus_space_handle_t,
|
|
bus_size_t, u_int16_t *, bus_size_t);
|
|
void (*dbs_rm_4)(void *, bus_space_handle_t,
|
|
bus_size_t, u_int32_t *, bus_size_t);
|
|
void (*dbs_rm_8)(void *, bus_space_handle_t,
|
|
bus_size_t, u_int64_t *, bus_size_t);
|
|
|
|
/* read region */
|
|
void (*dbs_rr_1)(void *, bus_space_handle_t,
|
|
bus_size_t, u_int8_t *, bus_size_t);
|
|
void (*dbs_rr_2)(void *, bus_space_handle_t,
|
|
bus_size_t, u_int16_t *, bus_size_t);
|
|
void (*dbs_rr_4)(void *, bus_space_handle_t,
|
|
bus_size_t, u_int32_t *, bus_size_t);
|
|
void (*dbs_rr_8)(void *, bus_space_handle_t,
|
|
bus_size_t, u_int64_t *, bus_size_t);
|
|
|
|
/* write (single) */
|
|
void (*dbs_w_1)(void *, bus_space_handle_t,
|
|
bus_size_t, u_int8_t);
|
|
void (*dbs_w_2)(void *, bus_space_handle_t,
|
|
bus_size_t, u_int16_t);
|
|
void (*dbs_w_4)(void *, bus_space_handle_t,
|
|
bus_size_t, u_int32_t);
|
|
void (*dbs_w_8)(void *, bus_space_handle_t,
|
|
bus_size_t, u_int64_t);
|
|
|
|
/* write multiple */
|
|
void (*dbs_wm_1)(void *, bus_space_handle_t,
|
|
bus_size_t, const u_int8_t *, bus_size_t);
|
|
void (*dbs_wm_2)(void *, bus_space_handle_t,
|
|
bus_size_t, const u_int16_t *, bus_size_t);
|
|
void (*dbs_wm_4)(void *, bus_space_handle_t,
|
|
bus_size_t, const u_int32_t *, bus_size_t);
|
|
void (*dbs_wm_8)(void *, bus_space_handle_t,
|
|
bus_size_t, const u_int64_t *, bus_size_t);
|
|
|
|
/* write region */
|
|
void (*dbs_wr_1)(void *, bus_space_handle_t,
|
|
bus_size_t, const u_int8_t *, bus_size_t);
|
|
void (*dbs_wr_2)(void *, bus_space_handle_t,
|
|
bus_size_t, const u_int16_t *, bus_size_t);
|
|
void (*dbs_wr_4)(void *, bus_space_handle_t,
|
|
bus_size_t, const u_int32_t *, bus_size_t);
|
|
void (*dbs_wr_8)(void *, bus_space_handle_t,
|
|
bus_size_t, const u_int64_t *, bus_size_t);
|
|
|
|
/* set multiple */
|
|
void (*dbs_sm_1)(void *, bus_space_handle_t,
|
|
bus_size_t, u_int8_t, bus_size_t);
|
|
void (*dbs_sm_2)(void *, bus_space_handle_t,
|
|
bus_size_t, u_int16_t, bus_size_t);
|
|
void (*dbs_sm_4)(void *, bus_space_handle_t,
|
|
bus_size_t, u_int32_t, bus_size_t);
|
|
void (*dbs_sm_8)(void *, bus_space_handle_t,
|
|
bus_size_t, u_int64_t, bus_size_t);
|
|
|
|
/* set region */
|
|
void (*dbs_sr_1)(void *, bus_space_handle_t,
|
|
bus_size_t, u_int8_t, bus_size_t);
|
|
void (*dbs_sr_2)(void *, bus_space_handle_t,
|
|
bus_size_t, u_int16_t, bus_size_t);
|
|
void (*dbs_sr_4)(void *, bus_space_handle_t,
|
|
bus_size_t, u_int32_t, bus_size_t);
|
|
void (*dbs_sr_8)(void *, bus_space_handle_t,
|
|
bus_size_t, u_int64_t, bus_size_t);
|
|
|
|
/* copy */
|
|
void (*dbs_c_1)(void *, bus_space_handle_t, bus_size_t,
|
|
bus_space_handle_t, bus_size_t, bus_size_t);
|
|
void (*dbs_c_2)(void *, bus_space_handle_t, bus_size_t,
|
|
bus_space_handle_t, bus_size_t, bus_size_t);
|
|
void (*dbs_c_4)(void *, bus_space_handle_t, bus_size_t,
|
|
bus_space_handle_t, bus_size_t, bus_size_t);
|
|
void (*dbs_c_8)(void *, bus_space_handle_t, bus_size_t,
|
|
bus_space_handle_t, bus_size_t, bus_size_t);
|
|
};
|
|
|
|
#ifdef _KERNEL
|
|
/*
|
|
* Utility macros; INTERNAL USE ONLY.
|
|
*/
|
|
#define __dbs_c(a,b) __CONCAT(a,b)
|
|
#define __dbs_opname(op,size) __dbs_c(__dbs_c(__dbs_c(dbs_,op),_),size)
|
|
|
|
#define __dbs_rs(sz, tn, t, h, o) \
|
|
(__BUS_SPACE_ADDRESS_SANITY((h) + (o), tn, "bus addr"), \
|
|
(*(t)->__dbs_opname(r,sz))((t)->dbs_cookie, h, o))
|
|
|
|
#define __dbs_ws(sz, tn, t, h, o, v) \
|
|
do { \
|
|
__BUS_SPACE_ADDRESS_SANITY((h) + (o), tn, "bus addr"); \
|
|
(*(t)->__dbs_opname(w,sz))((t)->dbs_cookie, h, o, v); \
|
|
} while (0)
|
|
|
|
#define __dbs_nonsingle(type, sz, tn, t, h, o, a, c) \
|
|
do { \
|
|
__BUS_SPACE_ADDRESS_SANITY((a), tn, "buffer"); \
|
|
__BUS_SPACE_ADDRESS_SANITY((h) + (o), tn, "bus addr"); \
|
|
(*(t)->__dbs_opname(type,sz))((t)->dbs_cookie, h, o, a, c); \
|
|
} while (0)
|
|
|
|
#define __dbs_set(type, sz, tn, t, h, o, v, c) \
|
|
do { \
|
|
__BUS_SPACE_ADDRESS_SANITY((h) + (o), tn, "bus addr"); \
|
|
(*(t)->__dbs_opname(type,sz))((t)->dbs_cookie, h, o, v, c); \
|
|
} while (0)
|
|
|
|
#define __dbs_copy(sz, tn, t, h1, o1, h2, o2, cnt) \
|
|
do { \
|
|
__BUS_SPACE_ADDRESS_SANITY((h1) + (o1), tn, "bus addr 1"); \
|
|
__BUS_SPACE_ADDRESS_SANITY((h2) + (o2), tn, "bus addr 2"); \
|
|
(*(t)->__dbs_opname(c,sz))((t)->dbs_cookie, h1, o1, h2, o2, cnt); \
|
|
} while (0)
|
|
|
|
|
|
/*
|
|
* Mapping and unmapping operations.
|
|
*/
|
|
#define bus_space_map(t, a, s, f, hp) \
|
|
(*(t)->dbs_map)((t)->dbs_cookie, (a), (s), (f), (hp))
|
|
#define bus_space_unmap(t, h, s) \
|
|
(*(t)->dbs_unmap)((t)->dbs_cookie, (h), (s))
|
|
#define bus_space_subregion(t, h, o, s, hp) \
|
|
(*(t)->dbs_subregion)((t)->dbs_cookie, (h), (o), (s), (hp))
|
|
|
|
#endif /* _KERNEL */
|
|
|
|
#define BUS_SPACE_MAP_CACHEABLE 0x01
|
|
#define BUS_SPACE_MAP_LINEAR 0x02
|
|
#define BUS_SPACE_MAP_PREFETCHABLE 0x04
|
|
|
|
#ifdef _KERNEL
|
|
/*
|
|
* Allocation and deallocation operations.
|
|
*/
|
|
#define bus_space_alloc(t, rs, re, s, a, b, f, ap, hp) \
|
|
(*(t)->dbs_alloc)((t)->dbs_cookie, (rs), (re), (s), (a), (b), \
|
|
(f), (ap), (hp))
|
|
#define bus_space_free(t, h, s) \
|
|
(*(t)->dbs_free)((t)->dbs_cookie, (h), (s))
|
|
|
|
/*
|
|
* Get kernel virtual address for ranges mapped BUS_SPACE_MAP_LINEAR.
|
|
*/
|
|
#define bus_space_vaddr(t, h) \
|
|
(*(t)->dbs_vaddr)((t)->dbs_cookie, (h))
|
|
|
|
/*
|
|
* Bus barrier operations. The Dreamcast does not currently require
|
|
* barriers, but we must provide the flags to MI code.
|
|
*/
|
|
#define bus_space_barrier(t, h, o, l, f) \
|
|
((void)((void)(t), (void)(h), (void)(o), (void)(l), (void)(f)))
|
|
|
|
#define BUS_SPACE_BARRIER_READ 0x01
|
|
#define BUS_SPACE_BARRIER_WRITE 0x02
|
|
|
|
|
|
/*
|
|
* Bus read (single) operations.
|
|
*/
|
|
#define bus_space_read_1(t, h, o) __dbs_rs(1,u_int8_t,(t),(h),(o))
|
|
#define bus_space_read_2(t, h, o) __dbs_rs(2,u_int16_t,(t),(h),(o))
|
|
#define bus_space_read_4(t, h, o) __dbs_rs(4,u_int32_t,(t),(h),(o))
|
|
#define bus_space_read_8(t, h, o) __dbs_rs(8,u_int64_t,(t),(h),(o))
|
|
|
|
|
|
/*
|
|
* Bus read multiple operations.
|
|
*/
|
|
#define bus_space_read_multi_1(t, h, o, a, c) \
|
|
__dbs_nonsingle(rm,1,u_int8_t,(t),(h),(o),(a),(c))
|
|
#define bus_space_read_multi_2(t, h, o, a, c) \
|
|
__dbs_nonsingle(rm,2,u_int16_t,(t),(h),(o),(a),(c))
|
|
#define bus_space_read_multi_4(t, h, o, a, c) \
|
|
__dbs_nonsingle(rm,4,u_int32_t,(t),(h),(o),(a),(c))
|
|
#define bus_space_read_multi_8(t, h, o, a, c) \
|
|
__dbs_nonsingle(rm,8,u_int64_t,(t),(h),(o),(a),(c))
|
|
|
|
|
|
/*
|
|
* Bus read region operations.
|
|
*/
|
|
#define bus_space_read_region_1(t, h, o, a, c) \
|
|
__dbs_nonsingle(rr,1,u_int8_t,(t),(h),(o),(a),(c))
|
|
#define bus_space_read_region_2(t, h, o, a, c) \
|
|
__dbs_nonsingle(rr,2,u_int16_t,(t),(h),(o),(a),(c))
|
|
#define bus_space_read_region_4(t, h, o, a, c) \
|
|
__dbs_nonsingle(rr,4,u_int32_t,(t),(h),(o),(a),(c))
|
|
#define bus_space_read_region_8(t, h, o, a, c) \
|
|
__dbs_nonsingle(rr,8,u_int64_t,(t),(h),(o),(a),(c))
|
|
|
|
|
|
/*
|
|
* Bus write (single) operations.
|
|
*/
|
|
#define bus_space_write_1(t, h, o, v) __dbs_ws(1,u_int8_t,(t),(h),(o),(v))
|
|
#define bus_space_write_2(t, h, o, v) __dbs_ws(2,u_int16_t,(t),(h),(o),(v))
|
|
#define bus_space_write_4(t, h, o, v) __dbs_ws(4,u_int32_t,(t),(h),(o),(v))
|
|
#define bus_space_write_8(t, h, o, v) __dbs_ws(8,u_int64_t,(t),(h),(o),(v))
|
|
|
|
|
|
/*
|
|
* Bus write multiple operations.
|
|
*/
|
|
#define bus_space_write_multi_1(t, h, o, a, c) \
|
|
__dbs_nonsingle(wm,1,u_int8_t,(t),(h),(o),(a),(c))
|
|
#define bus_space_write_multi_2(t, h, o, a, c) \
|
|
__dbs_nonsingle(wm,2,u_int16_t,(t),(h),(o),(a),(c))
|
|
#define bus_space_write_multi_4(t, h, o, a, c) \
|
|
__dbs_nonsingle(wm,4,u_int32_t,(t),(h),(o),(a),(c))
|
|
#define bus_space_write_multi_8(t, h, o, a, c) \
|
|
__dbs_nonsingle(wm,8,u_int64_t,(t),(h),(o),(a),(c))
|
|
|
|
|
|
/*
|
|
* Bus write region operations.
|
|
*/
|
|
#define bus_space_write_region_1(t, h, o, a, c) \
|
|
__dbs_nonsingle(wr,1,u_int8_t,(t),(h),(o),(a),(c))
|
|
#define bus_space_write_region_2(t, h, o, a, c) \
|
|
__dbs_nonsingle(wr,2,u_int16_t,(t),(h),(o),(a),(c))
|
|
#define bus_space_write_region_4(t, h, o, a, c) \
|
|
__dbs_nonsingle(wr,4,u_int32_t,(t),(h),(o),(a),(c))
|
|
#define bus_space_write_region_8(t, h, o, a, c) \
|
|
__dbs_nonsingle(wr,8,u_int64_t,(t),(h),(o),(a),(c))
|
|
|
|
|
|
/*
|
|
* Set multiple operations.
|
|
*/
|
|
#define bus_space_set_multi_1(t, h, o, v, c) \
|
|
__dbs_set(sm,1,u_int8_t,(t),(h),(o),(v),(c))
|
|
#define bus_space_set_multi_2(t, h, o, v, c) \
|
|
__dbs_set(sm,2,u_int16_t,(t),(h),(o),(v),(c))
|
|
#define bus_space_set_multi_4(t, h, o, v, c) \
|
|
__dbs_set(sm,4,u_int32_t,(t),(h),(o),(v),(c))
|
|
#define bus_space_set_multi_8(t, h, o, v, c) \
|
|
__dbs_set(sm,8,u_int64_t,(t),(h),(o),(v),(c))
|
|
|
|
|
|
/*
|
|
* Set region operations.
|
|
*/
|
|
#define bus_space_set_region_1(t, h, o, v, c) \
|
|
__dbs_set(sr,1,u_int8_t,(t),(h),(o),(v),(c))
|
|
#define bus_space_set_region_2(t, h, o, v, c) \
|
|
__dbs_set(sr,2,u_int16_t,(t),(h),(o),(v),(c))
|
|
#define bus_space_set_region_4(t, h, o, v, c) \
|
|
__dbs_set(sr,4,u_int32_t,(t),(h),(o),(v),(c))
|
|
#define bus_space_set_region_8(t, h, o, v, c) \
|
|
__dbs_set(sr,8,u_int64_t,(t),(h),(o),(v),(c))
|
|
|
|
|
|
/*
|
|
* Copy region operations.
|
|
*/
|
|
#define bus_space_copy_region_1(t, h1, o1, h2, o2, c) \
|
|
__dbs_copy(1, u_int8_t, (t), (h1), (o1), (h2), (o2), (c))
|
|
#define bus_space_copy_region_2(t, h1, o1, h2, o2, c) \
|
|
__dbs_copy(2, u_int16_t, (t), (h1), (o1), (h2), (o2), (c))
|
|
#define bus_space_copy_region_4(t, h1, o1, h2, o2, c) \
|
|
__dbs_copy(4, u_int32_t, (t), (h1), (o1), (h2), (o2), (c))
|
|
#define bus_space_copy_region_8(t, h1, o1, h2, o2, c) \
|
|
__dbs_copy(8, u_int64_t, (t), (h1), (o1), (h2), (o2), (c))
|
|
|
|
/*
|
|
* Bus stream operations--defined in terms of non-stream counterparts
|
|
*/
|
|
#define __BUS_SPACE_HAS_STREAM_METHODS 1
|
|
#define bus_space_read_stream_1 bus_space_read_1
|
|
#define bus_space_read_stream_2 bus_space_read_2
|
|
#define bus_space_read_stream_4 bus_space_read_4
|
|
#define bus_space_read_stream_8 bus_space_read_8
|
|
#define bus_space_read_multi_stream_1 bus_space_read_multi_1
|
|
#define bus_space_read_multi_stream_2 bus_space_read_multi_2
|
|
#define bus_space_read_multi_stream_4 bus_space_read_multi_4
|
|
#define bus_space_read_multi_stream_8 bus_space_read_multi_8
|
|
#define bus_space_read_region_stream_1 bus_space_read_region_1
|
|
#define bus_space_read_region_stream_2 bus_space_read_region_2
|
|
#define bus_space_read_region_stream_4 bus_space_read_region_4
|
|
#define bus_space_read_region_stream_8 bus_space_read_region_8
|
|
#define bus_space_write_stream_1 bus_space_write_1
|
|
#define bus_space_write_stream_2 bus_space_write_2
|
|
#define bus_space_write_stream_4 bus_space_write_4
|
|
#define bus_space_write_stream_8 bus_space_write_8
|
|
#define bus_space_write_multi_stream_1 bus_space_write_multi_1
|
|
#define bus_space_write_multi_stream_2 bus_space_write_multi_2
|
|
#define bus_space_write_multi_stream_4 bus_space_write_multi_4
|
|
#define bus_space_write_multi_stream_8 bus_space_write_multi_8
|
|
#define bus_space_write_region_stream_1 bus_space_write_region_1
|
|
#define bus_space_write_region_stream_2 bus_space_write_region_2
|
|
#define bus_space_write_region_stream_4 bus_space_write_region_4
|
|
#define bus_space_write_region_stream_8 bus_space_write_region_8
|
|
|
|
#endif /* _KERNEL */
|
|
|
|
/*
|
|
* Flags used in various bus DMA methods.
|
|
*/
|
|
#define BUS_DMA_WAITOK 0x000 /* safe to sleep (pseudo-flag) */
|
|
#define BUS_DMA_NOWAIT 0x001 /* not safe to sleep */
|
|
#define BUS_DMA_ALLOCNOW 0x002 /* perform resource allocation now */
|
|
#define BUS_DMA_COHERENT 0x004 /* map memory to not require sync */
|
|
#define BUS_DMA_STREAMING 0x008 /* hint: sequential, unidirectional */
|
|
#define BUS_DMA_BUS1 0x010 /* placeholders for bus functions... */
|
|
#define BUS_DMA_BUS2 0x020
|
|
#define BUS_DMA_BUS3 0x040
|
|
#define BUS_DMA_BUS4 0x080
|
|
#define BUS_DMA_READ 0x100 /* mapping is device -> memory only */
|
|
#define BUS_DMA_WRITE 0x200 /* mapping is memory -> device only */
|
|
#define BUS_DMA_NOCACHE 0x400 /* hint: map non-cached memory */
|
|
|
|
/* Forwards needed by prototypes below. */
|
|
struct mbuf;
|
|
struct uio;
|
|
|
|
/*
|
|
* Operations performed by bus_dmamap_sync().
|
|
*/
|
|
#define BUS_DMASYNC_PREREAD 0x01
|
|
#define BUS_DMASYNC_POSTREAD 0x02
|
|
#define BUS_DMASYNC_PREWRITE 0x04
|
|
#define BUS_DMASYNC_POSTWRITE 0x08
|
|
|
|
typedef struct dreamcast_bus_dma_tag *bus_dma_tag_t;
|
|
typedef struct dreamcast_bus_dmamap *bus_dmamap_t;
|
|
|
|
#define BUS_DMA_TAG_VALID(t) ((t) != (bus_dma_tag_t)0)
|
|
|
|
/*
|
|
* bus_dma_segment_t
|
|
*
|
|
* Describes a single contiguous DMA transaction. Values
|
|
* are suitable for programming into DMA registers.
|
|
*/
|
|
struct dreamcast_bus_dma_segment {
|
|
bus_addr_t ds_addr; /* DMA address */
|
|
bus_size_t ds_len; /* length of transfer */
|
|
};
|
|
typedef struct dreamcast_bus_dma_segment bus_dma_segment_t;
|
|
|
|
/*
|
|
* bus_dma_tag_t
|
|
*
|
|
* A machine-dependent opaque type describing the implementation of
|
|
* DMA for a given bus.
|
|
*/
|
|
|
|
struct dreamcast_bus_dma_tag {
|
|
void *_cookie; /* cookie used in the guts */
|
|
|
|
/*
|
|
* DMA mapping methods.
|
|
*/
|
|
int (*_dmamap_create)(bus_dma_tag_t, bus_size_t, int,
|
|
bus_size_t, bus_size_t, int, bus_dmamap_t *);
|
|
void (*_dmamap_destroy)(bus_dma_tag_t, bus_dmamap_t);
|
|
int (*_dmamap_load)(bus_dma_tag_t, bus_dmamap_t, void *,
|
|
bus_size_t, struct proc *, int);
|
|
int (*_dmamap_load_mbuf)(bus_dma_tag_t, bus_dmamap_t,
|
|
struct mbuf *, int);
|
|
int (*_dmamap_load_uio)(bus_dma_tag_t, bus_dmamap_t,
|
|
struct uio *, int);
|
|
int (*_dmamap_load_raw)(bus_dma_tag_t, bus_dmamap_t,
|
|
bus_dma_segment_t *, int, bus_size_t, int);
|
|
void (*_dmamap_unload)(bus_dma_tag_t, bus_dmamap_t);
|
|
void (*_dmamap_sync)(bus_dma_tag_t, bus_dmamap_t,
|
|
bus_addr_t, bus_size_t, int);
|
|
|
|
/*
|
|
* DMA memory utility functions.
|
|
*/
|
|
int (*_dmamem_alloc)(bus_dma_tag_t, bus_size_t, bus_size_t,
|
|
bus_size_t, bus_dma_segment_t *, int, int *, int);
|
|
void (*_dmamem_free)(bus_dma_tag_t,
|
|
bus_dma_segment_t *, int);
|
|
int (*_dmamem_map)(bus_dma_tag_t, bus_dma_segment_t *,
|
|
int, size_t, caddr_t *, int);
|
|
void (*_dmamem_unmap)(bus_dma_tag_t, caddr_t, size_t);
|
|
paddr_t (*_dmamem_mmap)(bus_dma_tag_t, bus_dma_segment_t *,
|
|
int, off_t, int, int);
|
|
};
|
|
|
|
#define bus_dmamap_create(t, s, n, m, b, f, p) \
|
|
(*(t)->_dmamap_create)((t), (s), (n), (m), (b), (f), (p))
|
|
#define bus_dmamap_destroy(t, p) \
|
|
(*(t)->_dmamap_destroy)((t), (p))
|
|
#define bus_dmamap_load(t, m, b, s, p, f) \
|
|
(*(t)->_dmamap_load)((t), (m), (b), (s), (p), (f))
|
|
#define bus_dmamap_load_mbuf(t, m, b, f) \
|
|
(*(t)->_dmamap_load_mbuf)((t), (m), (b), (f))
|
|
#define bus_dmamap_load_uio(t, m, u, f) \
|
|
(*(t)->_dmamap_load_uio)((t), (m), (u), (f))
|
|
#define bus_dmamap_load_raw(t, m, sg, n, s, f) \
|
|
(*(t)->_dmamap_load_raw)((t), (m), (sg), (n), (s), (f))
|
|
#define bus_dmamap_unload(t, p) \
|
|
(*(t)->_dmamap_unload)((t), (p))
|
|
#define bus_dmamap_sync(t, m, o, l, op) \
|
|
(void)((t)->_dmamap_sync ? \
|
|
(*(t)->_dmamap_sync)((t), (m), (o), (l), (op)) : (void)0)
|
|
|
|
#define bus_dmamem_alloc(t, s, a, b, sg, n, r, f) \
|
|
(*(t)->_dmamem_alloc)((t), (s), (a), (b), (sg), (n), (r), (f))
|
|
#define bus_dmamem_free(t, sg, n) \
|
|
(*(t)->_dmamem_free)((t), (sg), (n))
|
|
#define bus_dmamem_map(t, sg, n, s, k, f) \
|
|
(*(t)->_dmamem_map)((t), (sg), (n), (s), (k), (f))
|
|
#define bus_dmamem_unmap(t, k, s) \
|
|
(*(t)->_dmamem_unmap)((t), (k), (s))
|
|
#define bus_dmamem_mmap(t, sg, n, o, p, f) \
|
|
(*(t)->_dmamem_mmap)((t), (sg), (n), (o), (p), (f))
|
|
|
|
/*
|
|
* bus_dmamap_t
|
|
*
|
|
* Describes a DMA mapping.
|
|
*/
|
|
struct dreamcast_bus_dmamap {
|
|
/*
|
|
* PRIVATE MEMBERS: not for use my machine-independent code.
|
|
*/
|
|
bus_size_t _dm_size; /* largest DMA transfer mappable */
|
|
int _dm_segcnt; /* number of segs this map can map */
|
|
bus_size_t _dm_maxsegsz; /* largest possible segment */
|
|
bus_size_t _dm_boundary; /* don't cross this */
|
|
int _dm_flags; /* misc. flags */
|
|
|
|
void *_dm_cookie; /* cookie for bus-specific functions */
|
|
|
|
/*
|
|
* PUBLIC MEMBERS: these are used by machine-independent code.
|
|
*/
|
|
int dm_nsegs; /* # valid segments in mapping */
|
|
bus_dma_segment_t dm_segs[1]; /* segments; variable length */
|
|
bus_size_t dm_mapsize; /* size of the mapping */
|
|
};
|
|
|
|
#endif /* _DREAMCAST_BUS_H_ */
|