170 lines
5.2 KiB
C
170 lines
5.2 KiB
C
/* $NetBSD: cpu_sh.c,v 1.7 2003/11/09 21:12:08 scw Exp $ */
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/*
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* Copyright 2002 Wasabi Systems, Inc.
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* All rights reserved.
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*
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* Written by Steve C. Woodford for Wasabi Systems, Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed for the NetBSD Project by
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* Wasabi Systems, Inc.
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* 4. The name of Wasabi Systems, Inc. may not be used to endorse
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* or promote products derived from this software without specific prior
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* written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* SH-5 CPU Module
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: cpu_sh.c,v 1.7 2003/11/09 21:12:08 scw Exp $");
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#include <sys/param.h>
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#include <sys/kernel.h>
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#include <sys/systm.h>
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#include <sys/device.h>
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#include <machine/bootparams.h>
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#include <machine/cacheops.h>
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#include <machine/cpu.h>
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#include <machine/bus.h>
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#include <machine/intr.h>
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#include <sh5/sh5/stb1var.h>
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#include <sh5/dev/superhywayvar.h>
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#include "locators.h"
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static int cpu_shmatch(struct device *, struct cfdata *, void *);
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static void cpu_shattach(struct device *, struct device *, void *);
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CFATTACH_DECL(cpu_sh, sizeof(struct device),
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cpu_shmatch, cpu_shattach, NULL, NULL);
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extern struct cfdriver cpu_cd;
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static void cpu_prcache(struct device *, struct sh5_cache_info *, const char *);
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/*ARGSUSED*/
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static int
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cpu_shmatch(struct device *parent, struct cfdata *cf, void *args)
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{
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struct superhyway_attach_args *sa = args;
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if (strcmp(sa->sa_name, cpu_cd.cd_name))
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return (0);
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if (cf->cf_loc[SUPERHYWAYCF_PPORT] != bootparams.bp_cpu[0].pport)
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return (0);
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sa->sa_pport = cf->cf_loc[SUPERHYWAYCF_PPORT];
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return (1);
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}
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/*ARGSUSED*/
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static void
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cpu_shattach(struct device *parent, struct device *self, void *args)
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{
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struct superhyway_attach_args *sa = args;
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bus_space_handle_t bh;
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u_int64_t vcr;
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u_int cpuid, version;
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const char *cpustr;
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char str[64];
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bus_space_map(sa->sa_bust, SUPERHYWAY_PPORT_TO_BUSADDR(sa->sa_pport),
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SUPERHYWAY_REG_SZ, 0, &bh);
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vcr = bus_space_read_8(sa->sa_bust, bh, SUPERHYWAY_REG_VCR);
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bus_space_unmap(sa->sa_bust, bh, SUPERHYWAY_REG_SZ);
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/*
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* There seems to be a hardware bug which causes reads of CPU.VCR
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* to return zero under certain circumstances.
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*/
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if (vcr == 0) {
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cpuid = bootparams.bp_cpu[0].cpuid;
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version = bootparams.bp_cpu[0].version;
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} else {
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cpuid = SUPERHYWAY_VCR_MOD_ID(vcr);
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version = SUPERHYWAY_VCR_MOD_VERS(vcr);
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}
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switch (cpuid) {
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case SH5_CPUID_STB1:
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cpustr = "SH5 STB1 Evaluation Silicon";
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break;
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default:
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sprintf(str, "Unknown CPU ID: 0x%x", cpuid);
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cpustr = str;
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break;
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}
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printf("\n%s: %s, Version %d, %ld.%02ld MHz\n", self->dv_xname, cpustr,
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version, (long)(bootparams.bp_cpu[0].speed / 1000000),
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(long)(bootparams.bp_cpu[0].speed % 1000000) / 10000);
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if (sh5_cache_ops.iinfo.type == SH5_CACHE_INFO_TYPE_NONE) {
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/* Unified cache. */
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cpu_prcache(self, &sh5_cache_ops.dinfo, "Unified");
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} else {
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/* Separate I/D caches */
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cpu_prcache(self, &sh5_cache_ops.dinfo, "D");
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cpu_prcache(self, &sh5_cache_ops.iinfo, "I");
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}
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}
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static void
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cpu_prcache(struct device *dv, struct sh5_cache_info *ci, const char *name)
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{
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static const char *ctype[] = {NULL, "VIVT", "VIPT", "PIPT"};
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static const char *wtype[] = {NULL, "thru", "back"};
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int i;
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i = (strcmp(name, "I") == 0);
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if (ci->type == 0 || ci->type >= (sizeof(ctype)/sizeof(char *))) {
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printf("%s: WARNING: Invalid %s-cache type: %d\n",
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dv->dv_xname, name, ci->type);
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ci->type = SH5_CACHE_INFO_TYPE_VIVT; /* XXX: Safe default */
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}
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if (i == 0 &&
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(ci->write == 0 || ci->write >= (sizeof(wtype)/sizeof(char *)))) {
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printf("%s: WARNING: Invalid %s-cache write type: %d\n",
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dv->dv_xname, name, ci->write);
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ci->write = SH5_CACHE_INFO_WRITE_BACK; /* XXX: Safe default */
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}
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printf("%s: %s-cache %d KB %db/line %d-way %d-sets %s", dv->dv_xname,
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name, ci->size / 1024, ci->line_size, ci->nways,
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ci->nsets, ctype[ci->type]);
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if (i == 0)
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printf(" write-%s", wtype[ci->write]);
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printf("\n");
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}
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