89 lines
3.1 KiB
C
89 lines
3.1 KiB
C
/* $NetBSD: cia_swiz_bus_mem.c,v 1.15 1997/09/02 13:19:22 thorpej Exp $ */
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/*
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* Copyright (c) 1996 Carnegie-Mellon University.
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* All rights reserved.
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*
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* Author: Chris G. Demetriou
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*
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* Permission to use, copy, modify and distribute this software and
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* its documentation is hereby granted, provided that both the copyright
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* notice and this permission notice appear in all copies of the
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* software, derivative works or modified versions, and any portions
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* thereof, and that both notices appear in supporting documentation.
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*
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* CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
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* CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
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* FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
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*
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* Carnegie Mellon requests users of this software to return to
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*
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* Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
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* School of Computer Science
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* Carnegie Mellon University
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* Pittsburgh PA 15213-3890
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*
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* any improvements or extensions that they make and grant Carnegie the
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* rights to redistribute these changes.
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*/
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#include <sys/cdefs.h> /* RCS ID & Copyright macro defns */
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__KERNEL_RCSID(1, "$NetBSD: cia_swiz_bus_mem.c,v 1.15 1997/09/02 13:19:22 thorpej Exp $");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/malloc.h>
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#include <sys/syslog.h>
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#include <sys/device.h>
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#include <vm/vm.h>
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#include <machine/bus.h>
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#include <alpha/pci/ciareg.h>
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#include <alpha/pci/ciavar.h>
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#define CHIP cia_swiz
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#define CHIP_EX_MALLOC_SAFE(v) (((struct cia_config *)(v))->cc_mallocsafe)
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#define CHIP_D_MEM_EXTENT(v) (((struct cia_config *)(v))->cc_d_mem_ex)
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#define CHIP_S_MEM_EXTENT(v) (((struct cia_config *)(v))->cc_s_mem_ex)
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/* Dense region 1 */
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#define CHIP_D_MEM_W1_BUS_START(v) 0x00000000UL
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#define CHIP_D_MEM_W1_BUS_END(v) 0xffffffffUL
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#define CHIP_D_MEM_W1_SYS_START(v) CIA_PCI_DENSE
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#define CHIP_D_MEM_W1_SYS_END(v) (CIA_PCI_DENSE + 0xffffffffUL)
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/* Sparse region 1 */
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#define CHIP_S_MEM_W1_BUS_START(v) \
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HAE_MEM_REG1_START(((struct cia_config *)(v))->cc_hae_mem)
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#define CHIP_S_MEM_W1_BUS_END(v) \
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(CHIP_S_MEM_W1_BUS_START(v) + HAE_MEM_REG1_MASK)
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#define CHIP_S_MEM_W1_SYS_START(v) \
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CIA_PCI_SMEM1
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#define CHIP_S_MEM_W1_SYS_END(v) \
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(CIA_PCI_SMEM1 + ((HAE_MEM_REG1_MASK + 1) << 5) - 1)
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/* Sparse region 2 */
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#define CHIP_S_MEM_W2_BUS_START(v) \
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HAE_MEM_REG2_START(((struct cia_config *)(v))->cc_hae_mem)
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#define CHIP_S_MEM_W2_BUS_END(v) \
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(CHIP_S_MEM_W2_BUS_START(v) + HAE_MEM_REG2_MASK)
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#define CHIP_S_MEM_W2_SYS_START(v) \
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CIA_PCI_SMEM2
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#define CHIP_S_MEM_W2_SYS_END(v) \
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(CIA_PCI_SMEM2 + ((HAE_MEM_REG2_MASK + 1) << 5) - 1)
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/* Sparse region 3 */
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#define CHIP_S_MEM_W3_BUS_START(v) \
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HAE_MEM_REG3_START(((struct cia_config *)(v))->cc_hae_mem)
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#define CHIP_S_MEM_W3_BUS_END(v) \
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(CHIP_S_MEM_W3_BUS_START(v) + HAE_MEM_REG3_MASK)
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#define CHIP_S_MEM_W3_SYS_START(v) \
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CIA_PCI_SMEM3
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#define CHIP_S_MEM_W3_SYS_END(v) \
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(CIA_PCI_SMEM3 + ((HAE_MEM_REG3_MASK + 1) << 5) - 1)
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#include <alpha/pci/pci_swiz_bus_mem_chipdep.c>
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