7490f93305
Switch to CFATTACH_DECL_NEW/device_t/cfdata_t Defer attaching interrupt evcnts. Approved by releng.
224 lines
6.0 KiB
C
224 lines
6.0 KiB
C
/* $NetBSD: i80321_aau.c,v 1.15 2012/02/12 16:31:01 matt Exp $ */
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/*
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* Copyright (c) 2002 Wasabi Systems, Inc.
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* All rights reserved.
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*
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* Written by Jason R. Thorpe for Wasabi Systems, Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed for the NetBSD Project by
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* Wasabi Systems, Inc.
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* 4. The name of Wasabi Systems, Inc. may not be used to endorse
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* or promote products derived from this software without specific prior
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* written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Intel i80321 I/O Processor application accelerator unit support.
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: i80321_aau.c,v 1.15 2012/02/12 16:31:01 matt Exp $");
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#include <sys/param.h>
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#include <sys/pool.h>
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#include <sys/systm.h>
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#include <sys/device.h>
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#include <sys/uio.h>
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#include <sys/bus.h>
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#include <sys/intr.h>
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#include <uvm/uvm.h>
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#include <arm/xscale/i80321reg.h>
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#include <arm/xscale/i80321var.h>
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#include <arm/xscale/iopaaureg.h>
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#include <arm/xscale/iopaauvar.h>
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struct aau321_softc {
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/* Shared AAU definitions. */
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struct iopaau_softc sc_iopaau;
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/* i80321-specific stuff. */
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void *sc_error_ih;
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void *sc_eoc_ih;
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void *sc_eot_ih;
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};
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static struct iopaau_function aau321_func_zero = {
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.af_setup = iopaau_func_zero_setup,
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};
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static struct iopaau_function aau321_func_fill8 = {
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.af_setup = iopaau_func_fill8_setup,
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};
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static struct iopaau_function aau321_func_xor_1_4 = {
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.af_setup = iopaau_func_xor_setup,
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};
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static struct iopaau_function aau321_func_xor_5_8 = {
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.af_setup = iopaau_func_xor_setup,
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};
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static const struct dmover_algdesc aau321_algdescs[] = {
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{
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.dad_name = DMOVER_FUNC_ZERO,
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.dad_data = &aau321_func_zero,
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.dad_ninputs = 0
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},
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{
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.dad_name = DMOVER_FUNC_FILL8,
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.dad_data = &aau321_func_fill8,
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.dad_ninputs = 0
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},
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{
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.dad_name = DMOVER_FUNC_COPY,
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.dad_data = &aau321_func_xor_1_4,
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.dad_ninputs = 1
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},
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{
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.dad_name = DMOVER_FUNC_XOR2,
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.dad_data = &aau321_func_xor_1_4,
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.dad_ninputs = 2
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},
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{
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.dad_name = DMOVER_FUNC_XOR3,
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.dad_data = &aau321_func_xor_1_4,
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.dad_ninputs = 3
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},
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{
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.dad_name = DMOVER_FUNC_XOR4,
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.dad_data = &aau321_func_xor_1_4,
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.dad_ninputs = 4
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},
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{
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.dad_name = DMOVER_FUNC_XOR5,
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.dad_data = &aau321_func_xor_5_8,
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5
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},
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{
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.dad_name = DMOVER_FUNC_XOR6,
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.dad_data = &aau321_func_xor_5_8,
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.dad_ninputs = 6
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},
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{
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.dad_name = DMOVER_FUNC_XOR7,
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.dad_data = &aau321_func_xor_5_8,
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.dad_ninputs = 7
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},
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{
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.dad_name = DMOVER_FUNC_XOR8,
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.dad_data = &aau321_func_xor_5_8,
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.dad_ninputs = 8
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},
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};
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#define AAU321_ALGDESC_COUNT __arraycount(aau321_algdescs)
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static int
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aau321_match(device_t parent, cfdata_t match, void *aux)
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{
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struct iopxs_attach_args *ia = aux;
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if (strcmp(match->cf_name, ia->ia_name) == 0)
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return (1);
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return (0);
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}
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static void
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aau321_attach(device_t parent, device_t self, void *aux)
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{
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struct aau321_softc *sc321 = device_private(self);
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struct iopaau_softc *sc = &sc321->sc_iopaau;
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struct iopxs_attach_args *ia = aux;
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const char *xname = device_xname(self);
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int error;
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aprint_naive("\n");
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aprint_normal("\n");
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sc->sc_dev = self;
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sc->sc_st = ia->ia_st;
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error = bus_space_subregion(sc->sc_st, ia->ia_sh,
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ia->ia_offset, ia->ia_size, &sc->sc_sh);
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if (error) {
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aprint_error("%s: unable to subregion registers, error = %d\n",
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xname, error);
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return;
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}
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sc->sc_dmat = ia->ia_dmat;
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sc321->sc_error_ih = i80321_intr_establish(ICU_INT_AAUE, IPL_BIO,
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iopaau_intr, sc);
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if (sc321->sc_error_ih == NULL) {
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aprint_error("%s: unable to register error interrupt handler\n",
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xname);
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return;
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}
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sc321->sc_eoc_ih = i80321_intr_establish(ICU_INT_AAU_EOC, IPL_BIO,
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iopaau_intr, sc);
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if (sc321->sc_eoc_ih == NULL) {
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aprint_error("%s: unable to register EOC interrupt handler\n",
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xname);
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return;
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}
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sc321->sc_eot_ih = i80321_intr_establish(ICU_INT_AAU_EOT, IPL_BIO,
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iopaau_intr, sc);
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if (sc321->sc_eoc_ih == NULL) {
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aprint_error("%s: unable to register EOT interrupt handler\n",
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xname);
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return;
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}
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sc->sc_dmb.dmb_name = xname;
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sc->sc_dmb.dmb_speed = 1638400; /* XXX */
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sc->sc_dmb.dmb_cookie = sc;
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sc->sc_dmb.dmb_algdescs = aau321_algdescs;
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sc->sc_dmb.dmb_nalgdescs = AAU321_ALGDESC_COUNT;
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sc->sc_dmb.dmb_process = iopaau_process;
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iopaau_attach(sc);
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/*
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* These must be initialized after iopaau_attach()
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* because iopaau_desc_[48]_cache is set up there.
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*/
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KASSERT(iopaau_desc_4_cache != NULL);
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aau321_func_zero.af_desc_cache = iopaau_desc_4_cache;
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aau321_func_fill8.af_desc_cache = iopaau_desc_4_cache;
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aau321_func_xor_1_4.af_desc_cache = iopaau_desc_4_cache;
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KASSERT(iopaau_desc_8_cache != NULL);
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aau321_func_xor_5_8.af_desc_cache = iopaau_desc_8_cache;
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}
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CFATTACH_DECL_NEW(iopaau, sizeof(struct aau321_softc),
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aau321_match, aau321_attach, NULL, NULL);
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