85627b239f
xHCI controller. Adjustments to tegraxusbpad(4) will be needed to connect the controller to actual USB ports.
90 lines
3.9 KiB
C
90 lines
3.9 KiB
C
/* $NetBSD: tegra_xusbreg.h,v 1.1 2016/09/26 20:05:03 jakllsch Exp $ */
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/*
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* Copyright (c) 2016 Jonathan A. Kollasch
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
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* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
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* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _TEGRA_XUSBREG_H_
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#define _TEGRA_XUSBREG_H_
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/* in FPCI space */
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#define T_XUSB_CFG_ARU_MAILBOX_CMD_REG 0x0e4
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#define T_XUSB_CFG_ARU_MAILBOX_CMD_INT_EN __BIT(31)
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#define T_XUSB_CFG_ARU_MAILBOX_CMD_DEST_XHCI __BIT(30)
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#define T_XUSB_CFG_ARU_MAILBOX_CMD_DEST_SMI __BIT(29)
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#define T_XUSB_CFG_ARU_MAILBOX_CMD_DEST_PME __BIT(28)
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#define T_XUSB_CFG_ARU_MAILBOX_CMD_DEST_FALCON __BIT(27)
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#define T_XUSB_CFG_ARU_MAILBOX_DATA_IN_REG 0x0e8
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#define MAILBOX_DATA_DATA __BITS(23,0)
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#define MAILBOX_DATA_TYPE __BITS(31,24)
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#define T_XUSB_CFG_ARU_MAILBOX_DATA_OUT_REG 0x0ec
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#define T_XUSB_CFG_ARU_MAILBOX_OWNER_REG 0x0f0
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#define T_XUSB_CFG_ARU_MAILBOX_OWNER_ID __BITS(7,0)
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#define MAILBOX_OWNER_NONE 0
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#define MAILBOX_OWNER_FW 1
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#define MAILBOX_OWNER_SW 2
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#define T_XUSB_CFG_ARU_C11_CSBRANGE_REG 0x41c
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#define T_XUSB_CFG_ARU_C11_CSBRANGE_RANGE __BITS(31-9,9-9)
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#define T_XUSB_CFG_ARU_SMI_INTR_REG 0x428
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#define T_XUSB_CFG_ARU_SMI_INTR_EN __BIT(3)
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#define T_XUSB_CFG_ARU_SMI_INTR_FW_HANG __BIT(1)
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#define T_XUSB_CFG_CSB_BASE_ADDR 0x800
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#define XUSB_CSB_RANGE __BITS(31,9)
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#define XUSB_CSB_OFFSET __BITS(8,0)
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/* in CSB space via FPCI space*/
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#define XUSB_CSB_FALCON_CPUCTL_REG 0x100
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#define XUSB_CSB_FALCON_CPUCTL_STOPPED __BIT(5)
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#define XUSB_CSB_FALCON_CPUCTL_HALTED __BIT(4)
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#define XUSB_CSB_FALCON_CPUCTL_STARTCPU __BIT(1)
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#define XUSB_CSB_FALCON_BOOTVEC_REG 0x104
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#define XUSB_CSB_FALCON_DMACTL_REG 0x10c
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#define XUSB_CSB_FALCON_IMFILLRNG1_REG 0x154
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#define XUSB_CSB_FALCON_IMFILLRNG1_TAG_HI __BITS(31,16)
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#define XUSB_CSB_FALCON_IMFILLRNG1_TAG_LO __BITS(15,0)
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#define XUSB_CSB_FALCON_IMFILLCTL_REG 0x158
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#define XUSB_CSB_FALCON_IMFILLCTL_NBLOCKS __BITS(7,0)
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#define XUSB_CSB_MEMPOOL_APMAP_REG 0x10181c
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#define XUSB_CSB_MEMPOOL_APMAP_BOOTPATH __BIT(31)
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#define XUSB_CSB_MEMPOOL_ILOAD_ATTR_REG 0x101a00
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#define XUSB_CSB_MEMPOOL_ILOAD_BASE_LO_REG 0x101a04
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#define XUSB_CSB_MEMPOOL_ILOAD_BASE_LO_SRC_ADDR __BITS(7,0)
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#define XUSB_CSB_MEMPOOL_ILOAD_BASE_HI_REG 0x101a08
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#define XUSB_CSB_MEMPOOL_ILOAD_BASE_HI_SRC_ADDR __BITS(7,0)
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#define XUSB_CSB_MEMPOOL_L2IMEMOP_SIZE_REG 0x101a10
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#define XUSB_CSB_MEMPOOL_L2IMEMOP_SIZE_SRC_COUNT __BITS(31,24)
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#define XUSB_CSB_MEMPOOL_L2IMEMOP_SIZE_SRC_OFFSET __BITS(19,8)
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#define XUSB_CSB_MEMPOOL_L2IMEMOP_TRIG_REG 0x101a14
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#define XUSB_CSB_MEMPOOL_L2IMEMOP_TRIG_ACTION __BITS(31,24)
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#define ACTION_L2IMEM_LOAD_LOCKED_RESULT 0x11
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#define ACTION_L2IMEM_INVALIDATE_ALL 0x40
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#define IMEM_BLOCK_SIZE 256
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#endif /* _TEGRA_XUSBREG_H_ */
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