321 lines
10 KiB
C
321 lines
10 KiB
C
/* $NetBSD: tegra_usbphy.c,v 1.6 2016/03/08 07:49:20 skrll Exp $ */
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/*-
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* Copyright (c) 2015 Jared D. McNeill <jmcneill@invisible.ca>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: tegra_usbphy.c,v 1.6 2016/03/08 07:49:20 skrll Exp $");
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#include <sys/param.h>
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#include <sys/bus.h>
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#include <sys/device.h>
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#include <sys/intr.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#include <sys/atomic.h>
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#include <arm/nvidia/tegra_reg.h>
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#include <arm/nvidia/tegra_var.h>
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#include <arm/nvidia/tegra_usbreg.h>
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#include <dev/fdt/fdtvar.h>
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static int tegra_usbphy_match(device_t, cfdata_t, void *);
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static void tegra_usbphy_attach(device_t, device_t, void *);
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struct tegra_usbphy_softc {
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device_t sc_dev;
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bus_space_tag_t sc_bst;
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bus_space_handle_t sc_bsh;
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int sc_phandle;
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struct clk *sc_clk_reg;
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struct clk *sc_clk_pll;
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struct clk *sc_clk_utmip;
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struct fdtbus_reset *sc_rst_usb;
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struct fdtbus_reset *sc_rst_utmip;
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struct tegra_gpio_pin *sc_pin_vbus;
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uint32_t sc_hssync_start_delay;
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uint32_t sc_idle_wait_delay;
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uint32_t sc_elastic_limit;
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uint32_t sc_term_range_adj;
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uint32_t sc_xcvr_setup;
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uint32_t sc_xcvr_lsfslew;
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uint32_t sc_xcvr_lsrslew;
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uint32_t sc_hssquelch_level;
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uint32_t sc_hsdiscon_level;
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uint32_t sc_xcvr_hsslew;
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};
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static int tegra_usbphy_parse_properties(struct tegra_usbphy_softc *);
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static void tegra_usbphy_utmip_init(struct tegra_usbphy_softc *);
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CFATTACH_DECL_NEW(tegra_usbphy, sizeof(struct tegra_usbphy_softc),
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tegra_usbphy_match, tegra_usbphy_attach, NULL, NULL);
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static int
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tegra_usbphy_match(device_t parent, cfdata_t cf, void *aux)
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{
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const char * const compatible[] = { "nvidia,tegra124-usb-phy", NULL };
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struct fdt_attach_args * const faa = aux;
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return of_match_compatible(faa->faa_phandle, compatible);
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}
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static void
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tegra_usbphy_attach(device_t parent, device_t self, void *aux)
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{
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struct tegra_usbphy_softc * const sc = device_private(self);
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struct fdt_attach_args * const faa = aux;
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struct fdtbus_regulator *reg;
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const int phandle = faa->faa_phandle;
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bus_addr_t addr;
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bus_size_t size;
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int error;
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if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) {
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aprint_error(": couldn't get registers\n");
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return;
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}
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sc->sc_clk_reg = fdtbus_clock_get(phandle, "reg");
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if (sc->sc_clk_reg == NULL) {
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aprint_error(": couldn't get clock reg\n");
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return;
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}
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sc->sc_clk_pll = fdtbus_clock_get(phandle, "pll_u");
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if (sc->sc_clk_pll == NULL) {
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aprint_error(": couldn't get clock pll_u\n");
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return;
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}
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sc->sc_clk_utmip = fdtbus_clock_get(phandle, "utmi-pads");
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if (sc->sc_clk_utmip == NULL) {
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aprint_error(": couldn't get clock utmi-pads\n");
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return;
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}
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sc->sc_rst_usb = fdtbus_reset_get(phandle, "usb");
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if (sc->sc_rst_usb == NULL) {
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aprint_error(": couldn't get reset usb\n");
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return;
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}
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sc->sc_rst_utmip = fdtbus_reset_get(phandle, "utmi-pads");
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if (sc->sc_rst_utmip == NULL) {
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aprint_error(": couldn't get reset utmi-pads\n");
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return;
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}
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sc->sc_dev = self;
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sc->sc_phandle = phandle;
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sc->sc_bst = faa->faa_bst;
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error = bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh);
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if (error) {
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aprint_error(": couldn't map %#llx: %d", (uint64_t)addr, error);
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return;
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}
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aprint_naive("\n");
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aprint_normal(": USB PHY\n");
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if (tegra_usbphy_parse_properties(sc) != 0)
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return;
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fdtbus_reset_assert(sc->sc_rst_usb);
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error = clk_enable(sc->sc_clk_reg);
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if (error) {
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aprint_error_dev(self, "couldn't enable clock reg: %d\n",
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error);
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return;
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}
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fdtbus_reset_deassert(sc->sc_rst_usb);
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tegra_usbphy_utmip_init(sc);
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reg = fdtbus_regulator_acquire(phandle, "vbus-supply");
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if (reg) {
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const uint32_t v = bus_space_read_4(sc->sc_bst, sc->sc_bsh,
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TEGRA_EHCI_PHY_VBUS_SENSORS_REG);
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if ((v & TEGRA_EHCI_PHY_VBUS_SENSORS_A_VBUS_VLD_STS) == 0) {
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fdtbus_regulator_enable(reg);
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} else {
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aprint_normal_dev(self, "VBUS input active\n");
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}
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}
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}
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static int
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tegra_usbphy_parse_properties(struct tegra_usbphy_softc *sc)
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{
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#define PROPGET(k, v) \
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if (of_getprop_uint32(sc->sc_phandle, (k), (v))) { \
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aprint_error_dev(sc->sc_dev, \
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"missing property '%s'\n", (k)); \
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return EIO; \
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}
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PROPGET("nvidia,hssync-start-delay", &sc->sc_hssync_start_delay);
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PROPGET("nvidia,idle-wait-delay", &sc->sc_idle_wait_delay);
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PROPGET("nvidia,elastic-limit", &sc->sc_elastic_limit);
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PROPGET("nvidia,term-range-adj", &sc->sc_term_range_adj);
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PROPGET("nvidia,xcvr-setup", &sc->sc_xcvr_setup);
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PROPGET("nvidia,xcvr-lsfslew", &sc->sc_xcvr_lsfslew);
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PROPGET("nvidia,xcvr-lsrslew", &sc->sc_xcvr_lsrslew);
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PROPGET("nvidia,hssquelch-level", &sc->sc_hssquelch_level);
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PROPGET("nvidia,hsdiscon-level", &sc->sc_hsdiscon_level);
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PROPGET("nvidia,xcvr-hsslew", &sc->sc_xcvr_hsslew);
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return 0;
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#undef PROPGET
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}
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static void
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tegra_usbphy_utmip_init(struct tegra_usbphy_softc *sc)
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{
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bus_space_tag_t bst = sc->sc_bst;
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bus_space_handle_t bsh = sc->sc_bsh;
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int retry;
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/* Put UTMIP PHY into reset before programming UTMIP config registers */
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tegra_reg_set_clear(bst, bsh, TEGRA_EHCI_SUSP_CTRL_REG,
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TEGRA_EHCI_SUSP_CTRL_UTMIP_RESET, 0);
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/* Enable UTMIP PHY mode */
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tegra_reg_set_clear(bst, bsh, TEGRA_EHCI_SUSP_CTRL_REG,
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TEGRA_EHCI_SUSP_CTRL_UTMIP_PHY_ENB, 0);
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/* Stop crystal clock */
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tegra_reg_set_clear(bst, bsh, TEGRA_EHCI_UTMIP_MISC_CFG1_REG,
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0, TEGRA_EHCI_UTMIP_MISC_CFG1_PHY_XTAL_CLOCKEN);
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delay(1);
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/* Clear session status */
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tegra_reg_set_clear(bst, bsh, TEGRA_EHCI_PHY_VBUS_SENSORS_REG,
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0,
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TEGRA_EHCI_PHY_VBUS_SENSORS_B_VLD_SW_VALUE |
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TEGRA_EHCI_PHY_VBUS_SENSORS_B_VLD_SW_EN);
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/* Transceiver configuration */
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tegra_reg_set_clear(bst, bsh, TEGRA_EHCI_UTMIP_XCVR_CFG0_REG,
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__SHIFTIN(4, TEGRA_EHCI_UTMIP_XCVR_CFG0_SETUP) |
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__SHIFTIN(3, TEGRA_EHCI_UTMIP_XCVR_CFG0_SETUP_MSB) |
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__SHIFTIN(sc->sc_xcvr_hsslew,
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TEGRA_EHCI_UTMIP_XCVR_CFG0_HSSLEW_MSB),
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TEGRA_EHCI_UTMIP_XCVR_CFG0_SETUP |
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TEGRA_EHCI_UTMIP_XCVR_CFG0_SETUP_MSB |
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TEGRA_EHCI_UTMIP_XCVR_CFG0_HSSLEW_MSB);
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tegra_reg_set_clear(bst, bsh, TEGRA_EHCI_UTMIP_XCVR_CFG1_REG,
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__SHIFTIN(sc->sc_term_range_adj,
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TEGRA_EHCI_UTMIP_XCVR_CFG1_TERM_RANGE_ADJ),
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TEGRA_EHCI_UTMIP_XCVR_CFG1_TERM_RANGE_ADJ);
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if (of_getprop_bool(sc->sc_phandle, "nvidia,has-utmi-pad-registers")) {
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tegra_reg_set_clear(bst, bsh, TEGRA_EHCI_UTMIP_BIAS_CFG0_REG,
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TEGRA_EHCI_UTMIP_BIAS_CFG0_HSDISCON_LEVEL_MSB |
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__SHIFTIN(sc->sc_hsdiscon_level,
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TEGRA_EHCI_UTMIP_BIAS_CFG0_HSDISCON_LEVEL),
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TEGRA_EHCI_UTMIP_BIAS_CFG0_BIASPD |
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TEGRA_EHCI_UTMIP_BIAS_CFG0_HSDISCON_LEVEL);
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delay(25);
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tegra_reg_set_clear(bst, bsh, TEGRA_EHCI_UTMIP_BIAS_CFG1_REG,
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0, TEGRA_EHCI_UTMIP_BIAS_CFG1_PDTRK_POWERDOWN);
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}
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/* Misc config */
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tegra_reg_set_clear(bst, bsh, TEGRA_EHCI_UTMIP_MISC_CFG0_REG,
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0,
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TEGRA_EHCI_UTMIP_MISC_CFG0_SUSPEND_EXIT_ON_EDGE);
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/* BIAS cell power down lag */
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tegra_reg_set_clear(bst, bsh, TEGRA_EHCI_UTMIP_BIAS_CFG1_REG,
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__SHIFTIN(5, TEGRA_EHCI_UTMIP_BIAS_CFG1_PDTRK_COUNT),
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TEGRA_EHCI_UTMIP_BIAS_CFG1_PDTRK_COUNT);
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/* Debounce config */
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tegra_reg_set_clear(bst, bsh, TEGRA_EHCI_UTMIP_DEBOUNCE_CFG0_REG,
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__SHIFTIN(0x7530, TEGRA_EHCI_UTMIP_DEBOUNCE_CFG0_A),
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TEGRA_EHCI_UTMIP_DEBOUNCE_CFG0_A);
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/* Transmit signal preamble config */
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tegra_reg_set_clear(bst, bsh, TEGRA_EHCI_UTMIP_TX_CFG0_REG,
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TEGRA_EHCI_UTMIP_TX_CFG0_FS_PREAMBLE_J, 0);
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/* Power-down battery charger circuit */
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tegra_reg_set_clear(bst, bsh, TEGRA_EHCI_UTMIP_BAT_CHRG_CFG0_REG,
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TEGRA_EHCI_UTMIP_BAT_CHRG_CFG0_PD_CHRG, 0);
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/* Select low speed bias method */
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tegra_reg_set_clear(bst, bsh, TEGRA_EHCI_UTMIP_XCVR_CFG0_REG,
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0, TEGRA_EHCI_UTMIP_XCVR_CFG0_LSBIAS_SEL);
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/* High speed receive config */
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tegra_reg_set_clear(bst, bsh, TEGRA_EHCI_UTMIP_HSRX_CFG0_REG,
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__SHIFTIN(sc->sc_idle_wait_delay,
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TEGRA_EHCI_UTMIP_HSRX_CFG0_IDLE_WAIT) |
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__SHIFTIN(sc->sc_elastic_limit,
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TEGRA_EHCI_UTMIP_HSRX_CFG0_ELASTIC_LIMIT),
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TEGRA_EHCI_UTMIP_HSRX_CFG0_IDLE_WAIT |
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TEGRA_EHCI_UTMIP_HSRX_CFG0_ELASTIC_LIMIT);
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tegra_reg_set_clear(bst, bsh, TEGRA_EHCI_UTMIP_HSRX_CFG1_REG,
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__SHIFTIN(sc->sc_hssync_start_delay,
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TEGRA_EHCI_UTMIP_HSRX_CFG1_SYNC_START_DLY),
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TEGRA_EHCI_UTMIP_HSRX_CFG1_SYNC_START_DLY);
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/* Start crystal clock */
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delay(1);
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tegra_reg_set_clear(bst, bsh, TEGRA_EHCI_UTMIP_MISC_CFG1_REG,
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TEGRA_EHCI_UTMIP_MISC_CFG1_PHY_XTAL_CLOCKEN, 0);
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/* Bring UTMIP PHY out of reset */
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tegra_reg_set_clear(bst, bsh, TEGRA_EHCI_SUSP_CTRL_REG,
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0, TEGRA_EHCI_SUSP_CTRL_UTMIP_RESET);
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for (retry = 100000; retry > 0; retry--) {
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const uint32_t susp = bus_space_read_4(bst, bsh,
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TEGRA_EHCI_SUSP_CTRL_REG);
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if (susp & TEGRA_EHCI_SUSP_CTRL_PHY_CLK_VALID)
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break;
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delay(1);
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}
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if (retry == 0) {
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aprint_error_dev(sc->sc_dev, "PHY clock is not valid\n");
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return;
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}
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/* Disable ICUSB transceiver */
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tegra_reg_set_clear(bst, bsh, TEGRA_EHCI_ICUSB_CTRL_REG,
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0,
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TEGRA_EHCI_ICUSB_CTRL_ENB1);
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/* Power up UTMPI transceiver */
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tegra_reg_set_clear(bst, bsh, TEGRA_EHCI_UTMIP_XCVR_CFG0_REG,
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0,
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TEGRA_EHCI_UTMIP_XCVR_CFG0_PD_POWERDOWN |
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TEGRA_EHCI_UTMIP_XCVR_CFG0_PD2_POWERDOWN |
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TEGRA_EHCI_UTMIP_XCVR_CFG0_PDZI_POWERDOWN);
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tegra_reg_set_clear(bst, bsh, TEGRA_EHCI_UTMIP_XCVR_CFG1_REG,
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0,
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TEGRA_EHCI_UTMIP_XCVR_CFG1_PDDISC_POWERDOWN |
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TEGRA_EHCI_UTMIP_XCVR_CFG1_PDCHRP_POWERDOWN |
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TEGRA_EHCI_UTMIP_XCVR_CFG1_PDDR_POWERDOWN);
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}
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