94 lines
2.4 KiB
C
94 lines
2.4 KiB
C
/* $NetBSD: tegra_clock.h,v 1.1 2015/12/22 22:10:36 jmcneill Exp $ */
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/*-
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* Copyright (c) 2015 Jared D. McNeill <jmcneill@invisible.ca>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#ifndef _ARM_TEGRA_CLOCK_H
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#define _ARM_TEGRA_CLOCK_H
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enum tegra_clk_type {
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TEGRA_CLK_FIXED,
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TEGRA_CLK_PLL,
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TEGRA_CLK_MUX,
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TEGRA_CLK_FIXED_DIV,
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TEGRA_CLK_DIV,
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TEGRA_CLK_GATE
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};
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struct tegra_fixed_clk {
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u_int rate;
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};
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struct tegra_fixed_div_clk {
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u_int div;
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};
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struct tegra_pll_clk {
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u_int base_reg;
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u_int divm_mask;
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u_int divn_mask;
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u_int divp_mask;
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};
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struct tegra_mux_clk {
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const char **parents;
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u_int nparents;
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u_int reg;
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u_int bits;
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};
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struct tegra_div_clk {
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u_int reg;
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u_int bits;
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};
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struct tegra_gate_clk {
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u_int set_reg;
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u_int clr_reg;
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u_int bits;
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};
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struct tegra_clk {
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struct clk base; /* must be first */
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u_int id;
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const char *parent;
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enum tegra_clk_type type;
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u_int refcnt;
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union {
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struct tegra_fixed_clk fixed;
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struct tegra_pll_clk pll;
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struct tegra_mux_clk mux;
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struct tegra_fixed_div_clk fixed_div;
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struct tegra_div_clk div;
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struct tegra_gate_clk gate;
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} u;
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};
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#define TEGRA_CLK_BASE(_tclk) ((_tclk) ? &(_tclk)->base : NULL)
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#define TEGRA_CLK_PRIV(_clk) ((struct tegra_clk *)(_clk))
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#endif /* _ARM_TEGRA_CLOCK_H */
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