952 lines
24 KiB
C
952 lines
24 KiB
C
/* $NetBSD: pxa2x0_gpio.c,v 1.13 2009/08/04 12:11:33 kiyohara Exp $ */
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/*
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* Copyright 2003 Wasabi Systems, Inc.
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* All rights reserved.
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*
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* Written by Steve C. Woodford for Wasabi Systems, Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed for the NetBSD Project by
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* Wasabi Systems, Inc.
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* 4. The name of Wasabi Systems, Inc. may not be used to endorse
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* or promote products derived from this software without specific prior
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* written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: pxa2x0_gpio.c,v 1.13 2009/08/04 12:11:33 kiyohara Exp $");
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#include "opt_pxa2x0_gpio.h"
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/device.h>
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#include <sys/malloc.h>
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#include <machine/intr.h>
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#include <machine/bus.h>
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#include <arm/xscale/pxa2x0cpu.h>
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#include <arm/xscale/pxa2x0reg.h>
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#include <arm/xscale/pxa2x0var.h>
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#include <arm/xscale/pxa2x0_gpio.h>
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#include "locators.h"
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struct gpio_irq_handler {
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struct gpio_irq_handler *gh_next;
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int (*gh_func)(void *);
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void *gh_arg;
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int gh_spl;
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u_int gh_gpio;
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int gh_level;
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};
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struct pxagpio_softc {
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struct device sc_dev;
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bus_space_tag_t sc_bust;
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bus_space_handle_t sc_bush;
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void *sc_irqcookie[4];
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u_int32_t sc_mask[4];
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#ifdef PXAGPIO_HAS_GPION_INTRS
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struct gpio_irq_handler *sc_handlers[GPIO_NPINS];
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#else
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struct gpio_irq_handler *sc_handlers[2];
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#endif
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};
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static int pxagpio_match(struct device *, struct cfdata *, void *);
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static void pxagpio_attach(struct device *, struct device *, void *);
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CFATTACH_DECL(pxagpio, sizeof(struct pxagpio_softc),
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pxagpio_match, pxagpio_attach, NULL, NULL);
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static struct pxagpio_softc *pxagpio_softc;
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static vaddr_t pxagpio_regs;
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#define GPIO_BOOTSTRAP_REG(reg) \
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(*((volatile u_int32_t *)(pxagpio_regs + (reg))))
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static int gpio_intr0(void *);
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static int gpio_intr1(void *);
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#ifdef PXAGPIO_HAS_GPION_INTRS
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static int gpio_dispatch(struct pxagpio_softc *, int);
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static int gpio_intrN(void *);
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#endif
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static inline u_int32_t
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pxagpio_reg_read(struct pxagpio_softc *sc, int reg)
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{
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if (__predict_true(sc != NULL))
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return (bus_space_read_4(sc->sc_bust, sc->sc_bush, reg));
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else
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if (pxagpio_regs)
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return (GPIO_BOOTSTRAP_REG(reg));
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panic("pxagpio_reg_read: not bootstrapped");
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}
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static inline void
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pxagpio_reg_write(struct pxagpio_softc *sc, int reg, u_int32_t val)
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{
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if (__predict_true(sc != NULL))
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bus_space_write_4(sc->sc_bust, sc->sc_bush, reg, val);
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else
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if (pxagpio_regs)
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GPIO_BOOTSTRAP_REG(reg) = val;
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else
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panic("pxagpio_reg_write: not bootstrapped");
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return;
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}
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static int
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pxagpio_match(struct device *parent, struct cfdata *cf, void *aux)
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{
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struct pxaip_attach_args *pxa = aux;
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if (pxagpio_softc != NULL || pxa->pxa_addr != PXA2X0_GPIO_BASE)
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return (0);
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pxa->pxa_size = PXA2X0_GPIO_SIZE;
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return (1);
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}
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static void
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pxagpio_attach(struct device *parent, struct device *self, void *aux)
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{
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struct pxagpio_softc *sc = (struct pxagpio_softc *)self;
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struct pxaip_attach_args *pxa = aux;
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sc->sc_bust = pxa->pxa_iot;
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aprint_normal(": GPIO Controller\n");
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if (bus_space_map(sc->sc_bust, pxa->pxa_addr, pxa->pxa_size, 0,
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&sc->sc_bush)) {
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aprint_error("%s: Can't map registers!\n", sc->sc_dev.dv_xname);
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return;
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}
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pxagpio_regs = (vaddr_t)bus_space_vaddr(sc->sc_bust, sc->sc_bush);
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memset(sc->sc_handlers, 0, sizeof(sc->sc_handlers));
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/*
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* Disable all GPIO interrupts
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*/
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pxagpio_reg_write(sc, GPIO_GRER0, 0);
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pxagpio_reg_write(sc, GPIO_GRER1, 0);
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pxagpio_reg_write(sc, GPIO_GRER2, 0);
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pxagpio_reg_write(sc, GPIO_GFER0, 0);
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pxagpio_reg_write(sc, GPIO_GFER1, 0);
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pxagpio_reg_write(sc, GPIO_GFER2, 0);
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pxagpio_reg_write(sc, GPIO_GEDR0, ~0);
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pxagpio_reg_write(sc, GPIO_GEDR1, ~0);
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pxagpio_reg_write(sc, GPIO_GEDR2, ~0);
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#ifdef CPU_XSCALE_PXA270
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if (CPU_IS_PXA270) {
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pxagpio_reg_write(sc, GPIO_GRER3, 0);
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pxagpio_reg_write(sc, GPIO_GFER3, 0);
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pxagpio_reg_write(sc, GPIO_GEDR3, ~0);
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}
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#endif
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#ifdef PXAGPIO_HAS_GPION_INTRS
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sc->sc_irqcookie[2] = pxa2x0_intr_establish(PXA2X0_INT_GPION, IPL_BIO,
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gpio_intrN, sc);
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if (sc->sc_irqcookie[2] == NULL) {
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aprint_error("%s: failed to hook main GPIO interrupt\n",
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sc->sc_dev.dv_xname);
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return;
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}
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#endif
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sc->sc_irqcookie[0] = sc->sc_irqcookie[1] = NULL;
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pxagpio_softc = sc;
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}
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void
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pxa2x0_gpio_bootstrap(vaddr_t gpio_regs)
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{
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pxagpio_regs = gpio_regs;
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}
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void *
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pxa2x0_gpio_intr_establish(u_int gpio, int level, int spl, int (*func)(void *),
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void *arg)
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{
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struct pxagpio_softc *sc = pxagpio_softc;
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struct gpio_irq_handler *gh;
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u_int32_t bit, reg;
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#ifdef PXAGPIO_HAS_GPION_INTRS
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if (gpio >= GPIO_NPINS)
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panic("pxa2x0_gpio_intr_establish: bad pin number: %d", gpio);
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#else
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if (gpio > 1)
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panic("pxa2x0_gpio_intr_establish: bad pin number: %d", gpio);
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#endif
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if (!GPIO_IS_GPIO_IN(pxa2x0_gpio_get_function(gpio)))
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panic("pxa2x0_gpio_intr_establish: Pin %d not GPIO_IN", gpio);
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switch (level) {
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case IST_EDGE_FALLING:
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case IST_EDGE_RISING:
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case IST_EDGE_BOTH:
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break;
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default:
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panic("pxa2x0_gpio_intr_establish: bad level: %d", level);
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break;
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}
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if (sc->sc_handlers[gpio] != NULL)
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panic("pxa2x0_gpio_intr_establish: illegal shared interrupt");
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gh = malloc(sizeof(struct gpio_irq_handler), M_DEVBUF, M_NOWAIT);
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gh->gh_func = func;
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gh->gh_arg = arg;
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gh->gh_spl = spl;
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gh->gh_gpio = gpio;
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gh->gh_level = level;
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gh->gh_next = sc->sc_handlers[gpio];
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sc->sc_handlers[gpio] = gh;
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if (gpio == 0) {
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KDASSERT(sc->sc_irqcookie[0] == NULL);
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sc->sc_irqcookie[0] = pxa2x0_intr_establish(PXA2X0_INT_GPIO0,
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spl, gpio_intr0, sc);
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KDASSERT(sc->sc_irqcookie[0]);
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} else
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if (gpio == 1) {
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KDASSERT(sc->sc_irqcookie[1] == NULL);
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sc->sc_irqcookie[1] = pxa2x0_intr_establish(PXA2X0_INT_GPIO1,
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spl, gpio_intr1, sc);
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KDASSERT(sc->sc_irqcookie[1]);
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}
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bit = GPIO_BIT(gpio);
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sc->sc_mask[GPIO_BANK(gpio)] |= bit;
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switch (level) {
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case IST_EDGE_FALLING:
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reg = pxagpio_reg_read(sc, GPIO_REG(GPIO_GFER0, gpio));
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pxagpio_reg_write(sc, GPIO_REG(GPIO_GFER0, gpio), reg | bit);
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break;
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case IST_EDGE_RISING:
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reg = pxagpio_reg_read(sc, GPIO_REG(GPIO_GRER0, gpio));
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pxagpio_reg_write(sc, GPIO_REG(GPIO_GRER0, gpio), reg | bit);
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break;
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case IST_EDGE_BOTH:
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reg = pxagpio_reg_read(sc, GPIO_REG(GPIO_GFER0, gpio));
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pxagpio_reg_write(sc, GPIO_REG(GPIO_GFER0, gpio), reg | bit);
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reg = pxagpio_reg_read(sc, GPIO_REG(GPIO_GRER0, gpio));
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pxagpio_reg_write(sc, GPIO_REG(GPIO_GRER0, gpio), reg | bit);
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break;
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}
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return (gh);
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}
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void
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pxa2x0_gpio_intr_disestablish(void *cookie)
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{
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struct pxagpio_softc *sc = pxagpio_softc;
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struct gpio_irq_handler *gh = cookie;
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u_int32_t bit, reg;
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bit = GPIO_BIT(gh->gh_gpio);
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reg = pxagpio_reg_read(sc, GPIO_REG(GPIO_GFER0, gh->gh_gpio));
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reg &= ~bit;
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pxagpio_reg_write(sc, GPIO_REG(GPIO_GFER0, gh->gh_gpio), reg);
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reg = pxagpio_reg_read(sc, GPIO_REG(GPIO_GRER0, gh->gh_gpio));
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reg &= ~bit;
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pxagpio_reg_write(sc, GPIO_REG(GPIO_GRER0, gh->gh_gpio), reg);
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pxagpio_reg_write(sc, GPIO_REG(GPIO_GEDR0, gh->gh_gpio), bit);
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sc->sc_mask[GPIO_BANK(gh->gh_gpio)] &= ~bit;
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sc->sc_handlers[gh->gh_gpio] = NULL;
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if (gh->gh_gpio == 0) {
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#if 0
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pxa2x0_intr_disestablish(sc->sc_irqcookie[0]);
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sc->sc_irqcookie[0] = NULL;
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#else
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panic("pxa2x0_gpio_intr_disestablish: can't unhook GPIO#0");
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#endif
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} else
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if (gh->gh_gpio == 1) {
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#if 0
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pxa2x0_intr_disestablish(sc->sc_irqcookie[1]);
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sc->sc_irqcookie[1] = NULL;
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#else
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panic("pxa2x0_gpio_intr_disestablish: can't unhook GPIO#1");
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#endif
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}
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free(gh, M_DEVBUF);
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}
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static int
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gpio_intr0(void *arg)
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{
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struct pxagpio_softc *sc = arg;
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#ifdef DIAGNOSTIC
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if (sc->sc_handlers[0] == NULL) {
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printf("%s: stray GPIO#0 edge interrupt\n",
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sc->sc_dev.dv_xname);
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return (0);
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}
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#endif
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bus_space_write_4(sc->sc_bust, sc->sc_bush, GPIO_REG(GPIO_GEDR0, 0),
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GPIO_BIT(0));
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return ((sc->sc_handlers[0]->gh_func)(sc->sc_handlers[0]->gh_arg));
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}
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static int
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gpio_intr1(void *arg)
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{
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struct pxagpio_softc *sc = arg;
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#ifdef DIAGNOSTIC
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if (sc->sc_handlers[1] == NULL) {
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printf("%s: stray GPIO#1 edge interrupt\n",
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sc->sc_dev.dv_xname);
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return (0);
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}
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#endif
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bus_space_write_4(sc->sc_bust, sc->sc_bush, GPIO_REG(GPIO_GEDR0, 1),
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GPIO_BIT(1));
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return ((sc->sc_handlers[1]->gh_func)(sc->sc_handlers[1]->gh_arg));
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}
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#ifdef PXAGPIO_HAS_GPION_INTRS
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static int
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gpio_dispatch(struct pxagpio_softc *sc, int gpio_base)
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{
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struct gpio_irq_handler **ghp, *gh;
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int i, s, nhandled, handled, pins;
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u_int32_t gedr, mask;
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int bank;
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/* Fetch bitmap of pending interrupts on this GPIO bank */
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gedr = pxagpio_reg_read(sc, GPIO_REG(GPIO_GEDR0, gpio_base));
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/* Don't handle GPIO 0/1 here */
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if (gpio_base == 0)
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gedr &= ~(GPIO_BIT(0) | GPIO_BIT(1));
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/* Bail early if there are no pending interrupts in this bank */
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if (gedr == 0)
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return (0);
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/* Acknowledge pending interrupts. */
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pxagpio_reg_write(sc, GPIO_REG(GPIO_GEDR0, gpio_base), gedr);
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bank = GPIO_BANK(gpio_base);
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/*
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* We're only interested in those for which we have a handler
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* registered
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*/
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#ifdef DEBUG
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if ((gedr & sc->sc_mask[bank]) == 0) {
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printf("%s: stray GPIO interrupt. Bank %d, GEDR 0x%08x, mask 0x%08x\n",
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sc->sc_dev.dv_xname, bank, gedr, sc->sc_mask[bank]);
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return (1); /* XXX: Pretend we dealt with it */
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}
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#endif
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gedr &= sc->sc_mask[bank];
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ghp = &sc->sc_handlers[gpio_base];
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if (CPU_IS_PXA270)
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pins = (gpio_base < 96) ? 32 : 25;
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else
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pins = (gpio_base < 64) ? 32 : 17;
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handled = 0;
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for (i = 0, mask = 1; i < pins && gedr; i++, ghp++, mask <<= 1) {
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if ((gedr & mask) == 0)
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continue;
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gedr &= ~mask;
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if ((gh = *ghp) == NULL) {
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printf("%s: unhandled GPIO interrupt. GPIO#%d\n",
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sc->sc_dev.dv_xname, gpio_base + i);
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continue;
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}
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s = _splraise(gh->gh_spl);
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do {
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nhandled = (gh->gh_func)(gh->gh_arg);
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handled |= nhandled;
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gh = gh->gh_next;
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} while (gh != NULL);
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splx(s);
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}
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return (handled);
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}
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static int
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gpio_intrN(void *arg)
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{
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struct pxagpio_softc *sc = arg;
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int handled;
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handled = gpio_dispatch(sc, 0);
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handled |= gpio_dispatch(sc, 32);
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handled |= gpio_dispatch(sc, 64);
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if (CPU_IS_PXA270)
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handled |= gpio_dispatch(sc, 96);
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return (handled);
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}
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#endif /* PXAGPIO_HAS_GPION_INTRS */
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u_int
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pxa2x0_gpio_get_function(u_int gpio)
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{
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struct pxagpio_softc *sc = pxagpio_softc;
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u_int32_t rv, io;
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KDASSERT(gpio < GPIO_NPINS);
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rv = pxagpio_reg_read(sc, GPIO_FN_REG(gpio)) >> GPIO_FN_SHIFT(gpio);
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rv = GPIO_FN(rv);
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io = pxagpio_reg_read(sc, GPIO_REG(GPIO_GPDR0, gpio));
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if (io & GPIO_BIT(gpio))
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rv |= GPIO_OUT;
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io = pxagpio_reg_read(sc, GPIO_REG(GPIO_GPLR0, gpio));
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if (io & GPIO_BIT(gpio))
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rv |= GPIO_SET;
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return (rv);
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}
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u_int
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pxa2x0_gpio_set_function(u_int gpio, u_int fn)
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{
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struct pxagpio_softc *sc = pxagpio_softc;
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u_int32_t rv, bit;
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u_int oldfn;
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KDASSERT(gpio < GPIO_NPINS);
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oldfn = pxa2x0_gpio_get_function(gpio);
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if (GPIO_FN(fn) == GPIO_FN(oldfn) &&
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GPIO_FN_IS_OUT(fn) == GPIO_FN_IS_OUT(oldfn)) {
|
|
/*
|
|
* The pin's function is not changing.
|
|
* For Alternate Functions and GPIO input, we can just
|
|
* return now.
|
|
* For GPIO output pins, check the initial state is
|
|
* the same.
|
|
*
|
|
* Return 'fn' instead of 'oldfn' so the caller can
|
|
* reliably detect that we didn't change anything.
|
|
* (The initial state might be different for non-
|
|
* GPIO output pins).
|
|
*/
|
|
if (!GPIO_IS_GPIO_OUT(fn) ||
|
|
GPIO_FN_IS_SET(fn) == GPIO_FN_IS_SET(oldfn))
|
|
return (fn);
|
|
}
|
|
|
|
/*
|
|
* See section 4.1.3.7 of the PXA2x0 Developer's Manual for
|
|
* the correct procedure for changing GPIO pin functions.
|
|
*/
|
|
|
|
bit = GPIO_BIT(gpio);
|
|
|
|
/*
|
|
* 1. Configure the correct set/clear state of the pin
|
|
*/
|
|
if (GPIO_FN_IS_SET(fn))
|
|
pxagpio_reg_write(sc, GPIO_REG(GPIO_GPSR0, gpio), bit);
|
|
else
|
|
pxagpio_reg_write(sc, GPIO_REG(GPIO_GPCR0, gpio), bit);
|
|
|
|
/*
|
|
* 2. Configure the pin as an input or output as appropriate
|
|
*/
|
|
rv = pxagpio_reg_read(sc, GPIO_REG(GPIO_GPDR0, gpio)) & ~bit;
|
|
if (GPIO_FN_IS_OUT(fn))
|
|
rv |= bit;
|
|
pxagpio_reg_write(sc, GPIO_REG(GPIO_GPDR0, gpio), rv);
|
|
|
|
/*
|
|
* 3. Configure the pin's function
|
|
*/
|
|
bit = GPIO_FN_MASK << GPIO_FN_SHIFT(gpio);
|
|
fn = GPIO_FN(fn) << GPIO_FN_SHIFT(gpio);
|
|
rv = pxagpio_reg_read(sc, GPIO_FN_REG(gpio)) & ~bit;
|
|
pxagpio_reg_write(sc, GPIO_FN_REG(gpio), rv | fn);
|
|
|
|
return (oldfn);
|
|
}
|
|
|
|
/*
|
|
* Quick function to read pin value
|
|
*/
|
|
int
|
|
pxa2x0_gpio_get_bit(u_int gpio)
|
|
{
|
|
struct pxagpio_softc *sc = pxagpio_softc;
|
|
int bit;
|
|
|
|
bit = GPIO_BIT(gpio);
|
|
if (pxagpio_reg_read(sc, GPIO_REG(GPIO_GPLR0, gpio)) & bit)
|
|
return 1;
|
|
else
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* Quick function to set pin to 1
|
|
*/
|
|
void
|
|
pxa2x0_gpio_set_bit(u_int gpio)
|
|
{
|
|
struct pxagpio_softc *sc = pxagpio_softc;
|
|
int bit;
|
|
|
|
bit = GPIO_BIT(gpio);
|
|
pxagpio_reg_write(sc, GPIO_REG(GPIO_GPSR0, gpio), bit);
|
|
}
|
|
|
|
/*
|
|
* Quick function to set pin to 0
|
|
*/
|
|
void
|
|
pxa2x0_gpio_clear_bit(u_int gpio)
|
|
{
|
|
struct pxagpio_softc *sc = pxagpio_softc;
|
|
int bit;
|
|
|
|
bit = GPIO_BIT(gpio);
|
|
pxagpio_reg_write(sc, GPIO_REG(GPIO_GPCR0, gpio), bit);
|
|
}
|
|
|
|
/*
|
|
* Quick function to change pin direction
|
|
*/
|
|
void
|
|
pxa2x0_gpio_set_dir(u_int gpio, int dir)
|
|
{
|
|
struct pxagpio_softc *sc = pxagpio_softc;
|
|
int bit;
|
|
u_int32_t reg;
|
|
|
|
bit = GPIO_BIT(gpio);
|
|
|
|
reg = pxagpio_reg_read(sc, GPIO_REG(GPIO_GPDR0, gpio)) & ~bit;
|
|
if (GPIO_FN_IS_OUT(dir))
|
|
reg |= bit;
|
|
pxagpio_reg_write(sc, GPIO_REG(GPIO_GPDR0, gpio), reg);
|
|
}
|
|
|
|
/*
|
|
* Quick function to clear interrupt status on a pin
|
|
* GPIO pins may be toggle in an interrupt and we dont want
|
|
* extra spurious interrupts to occur.
|
|
* Suppose this causes a slight race if a key is pressed while
|
|
* the interrupt handler is running. (yes this is for the keyboard driver)
|
|
*/
|
|
void
|
|
pxa2x0_gpio_clear_intr(u_int gpio)
|
|
{
|
|
struct pxagpio_softc *sc = pxagpio_softc;
|
|
int bit;
|
|
|
|
bit = GPIO_BIT(gpio);
|
|
pxagpio_reg_write(sc, GPIO_REG(GPIO_GEDR0, gpio), bit);
|
|
}
|
|
|
|
/*
|
|
* Quick function to mask (disable) a GPIO interrupt
|
|
*/
|
|
void
|
|
pxa2x0_gpio_intr_mask(void *v)
|
|
{
|
|
struct gpio_irq_handler *gh = (struct gpio_irq_handler *)v;
|
|
|
|
pxa2x0_gpio_set_intr_level(gh->gh_gpio, IPL_NONE);
|
|
}
|
|
|
|
/*
|
|
* Quick function to unmask (enable) a GPIO interrupt
|
|
*/
|
|
void
|
|
pxa2x0_gpio_intr_unmask(void *v)
|
|
{
|
|
struct gpio_irq_handler *gh = (struct gpio_irq_handler *)v;
|
|
|
|
pxa2x0_gpio_set_intr_level(gh->gh_gpio, gh->gh_level);
|
|
}
|
|
|
|
/*
|
|
* Configure the edge sensitivity of interrupt pins
|
|
*/
|
|
void
|
|
pxa2x0_gpio_set_intr_level(u_int gpio, int level)
|
|
{
|
|
struct pxagpio_softc *sc = pxagpio_softc;
|
|
u_int32_t bit;
|
|
u_int32_t gfer;
|
|
u_int32_t grer;
|
|
int s;
|
|
|
|
s = splhigh();
|
|
|
|
bit = GPIO_BIT(gpio);
|
|
gfer = pxagpio_reg_read(sc, GPIO_REG(GPIO_GFER0, gpio));
|
|
grer = pxagpio_reg_read(sc, GPIO_REG(GPIO_GRER0, gpio));
|
|
|
|
switch (level) {
|
|
case IST_NONE:
|
|
gfer &= ~bit;
|
|
grer &= ~bit;
|
|
break;
|
|
case IST_EDGE_FALLING:
|
|
gfer |= bit;
|
|
grer &= ~bit;
|
|
break;
|
|
case IST_EDGE_RISING:
|
|
gfer &= ~bit;
|
|
grer |= bit;
|
|
break;
|
|
case IST_EDGE_BOTH:
|
|
gfer |= bit;
|
|
grer |= bit;
|
|
break;
|
|
default:
|
|
panic("pxa2x0_gpio_set_intr_level: bad level: %d", level);
|
|
break;
|
|
}
|
|
|
|
pxagpio_reg_write(sc, GPIO_REG(GPIO_GFER0, gpio), gfer);
|
|
pxagpio_reg_write(sc, GPIO_REG(GPIO_GRER0, gpio), grer);
|
|
|
|
splx(s);
|
|
}
|
|
|
|
|
|
#if defined(CPU_XSCALE_PXA250)
|
|
/*
|
|
* Configurations of GPIO for PXA25x
|
|
*/
|
|
struct pxa2x0_gpioconf pxa25x_com_btuart_gpioconf[] = {
|
|
{ 42, GPIO_CLR | GPIO_ALT_FN_1_IN }, /* BTRXD */
|
|
{ 43, GPIO_CLR | GPIO_ALT_FN_2_OUT }, /* BTTXD */
|
|
|
|
#if 0 /* optional */
|
|
{ 44, GPIO_CLR | GPIO_ALT_FN_1_IN }, /* BTCTS */
|
|
{ 45, GPIO_CLR | GPIO_ALT_FN_2_OUT }, /* BTRTS */
|
|
#endif
|
|
|
|
{ -1 }
|
|
};
|
|
|
|
struct pxa2x0_gpioconf pxa25x_com_ffuart_gpioconf[] = {
|
|
{ 34, GPIO_CLR | GPIO_ALT_FN_1_IN }, /* FFRXD */
|
|
|
|
#if 0 /* optional */
|
|
{ 35, GPIO_CLR | GPIO_ALT_FN_1_IN }, /* CTS */
|
|
{ 36, GPIO_CLR | GPIO_ALT_FN_1_IN }, /* DCD */
|
|
{ 37, GPIO_CLR | GPIO_ALT_FN_1_IN }, /* DSR */
|
|
{ 38, GPIO_CLR | GPIO_ALT_FN_1_IN }, /* RI */
|
|
#endif
|
|
|
|
{ 39, GPIO_CLR | GPIO_ALT_FN_2_OUT }, /* FFTXD */
|
|
|
|
#if 0 /* optional */
|
|
{ 40, GPIO_CLR | GPIO_ALT_FN_2_OUT }, /* DTR */
|
|
{ 41, GPIO_CLR | GPIO_ALT_FN_2_OUT }, /* RTS */
|
|
#endif
|
|
|
|
{ -1 }
|
|
};
|
|
|
|
struct pxa2x0_gpioconf pxa25x_com_hwuart_gpioconf[] = {
|
|
#if 0 /* We can select and/or. */
|
|
{ 42, GPIO_CLR | GPIO_ALT_FN_3_IN }, /* HWRXD */
|
|
{ 49, GPIO_CLR | GPIO_ALT_FN_2_IN }, /* HWRXD */
|
|
|
|
{ 43, GPIO_CLR | GPIO_ALT_FN_3_OUT }, /* HWTXD */
|
|
{ 48, GPIO_CLR | GPIO_ALT_FN_1_OUT }, /* HWTXD */
|
|
|
|
#if 0 /* optional */
|
|
{ 44, GPIO_CLR | GPIO_ALT_FN_3_IN }, /* HWCST */
|
|
{ 51, GPIO_CLR | GPIO_ALT_FN_3_IN }, /* HWCST */
|
|
|
|
{ 45, GPIO_CLR | GPIO_ALT_FN_3_OUT }, /* HWRST */
|
|
{ 52, GPIO_CLR | GPIO_ALT_FN_3_OUT }, /* HWRST */
|
|
#endif
|
|
#endif
|
|
|
|
{ -1 }
|
|
};
|
|
|
|
struct pxa2x0_gpioconf pxa25x_com_stuart_gpioconf[] = {
|
|
{ 46, GPIO_CLR | GPIO_ALT_FN_2_IN }, /* RXD */
|
|
{ 47, GPIO_CLR | GPIO_ALT_FN_1_OUT }, /* TXD */
|
|
{ -1 }
|
|
};
|
|
|
|
struct pxa2x0_gpioconf pxa25x_i2c_gpioconf[] = {
|
|
{ -1 }
|
|
};
|
|
|
|
struct pxa2x0_gpioconf pxa25x_i2s_gpioconf[] = {
|
|
{ 28, GPIO_CLR | GPIO_ALT_FN_1_OUT }, /* BITCLK */
|
|
{ 29, GPIO_CLR | GPIO_ALT_FN_2_IN }, /* SDATA_IN */
|
|
{ 30, GPIO_CLR | GPIO_ALT_FN_1_OUT }, /* SDATA_OUT */
|
|
{ 31, GPIO_CLR | GPIO_ALT_FN_1_OUT }, /* SYNC */
|
|
{ 32, GPIO_CLR | GPIO_ALT_FN_1_OUT }, /* SYSCLK */
|
|
{ -1 }
|
|
};
|
|
|
|
struct pxa2x0_gpioconf pxa25x_pcic_gpioconf[] = {
|
|
{ 48, GPIO_CLR | GPIO_ALT_FN_2_OUT }, /* nPOE */
|
|
{ 49, GPIO_CLR | GPIO_ALT_FN_2_OUT }, /* nPWE */
|
|
{ 50, GPIO_CLR | GPIO_ALT_FN_2_OUT }, /* nPIOR */
|
|
{ 51, GPIO_CLR | GPIO_ALT_FN_2_OUT }, /* nPIOW */
|
|
|
|
#if 0 /* We can select and/or. */
|
|
{ 52, GPIO_CLR | GPIO_ALT_FN_2_OUT }, /* nPCE1 */
|
|
{ 53, GPIO_CLR | GPIO_ALT_FN_2_OUT }, /* nPCE2 */
|
|
#endif
|
|
|
|
{ 54, GPIO_CLR | GPIO_ALT_FN_2_OUT }, /* pSKTSEL */
|
|
{ 55, GPIO_CLR | GPIO_ALT_FN_2_OUT }, /* nPREG */
|
|
{ 56, GPIO_CLR | GPIO_ALT_FN_1_IN }, /* nPWAIT */
|
|
{ 57, GPIO_CLR | GPIO_ALT_FN_1_IN }, /* nIOIS16 */
|
|
{ -1 }
|
|
};
|
|
|
|
struct pxa2x0_gpioconf pxa25x_pxaacu_gpioconf[] = {
|
|
{ 28, GPIO_CLR | GPIO_ALT_FN_1_IN }, /* BITCLK */
|
|
{ 30, GPIO_CLR | GPIO_ALT_FN_2_OUT }, /* SDATA_OUT */
|
|
{ 31, GPIO_CLR | GPIO_ALT_FN_2_OUT }, /* SYNC */
|
|
|
|
#if 0 /* We can select and/or. */
|
|
{ 29, GPIO_CLR | GPIO_ALT_FN_1_IN }, /* SDATA_IN0 */
|
|
{ 32, GPIO_CLR | GPIO_ALT_FN_1_IN }, /* SDATA_IN1 */
|
|
#endif
|
|
|
|
{ -1 }
|
|
};
|
|
|
|
struct pxa2x0_gpioconf pxa25x_pxamci_gpioconf[] = {
|
|
#if 0 /* We can select and/or. */
|
|
{ 6, GPIO_CLR | GPIO_ALT_FN_1_OUT }, /* MMCCLK */
|
|
{ 53, GPIO_CLR | GPIO_ALT_FN_1_OUT }, /* MMCCLK */
|
|
{ 54, GPIO_CLR | GPIO_ALT_FN_1_OUT }, /* MMCCLK */
|
|
|
|
{ 8, GPIO_CLR | GPIO_ALT_FN_1_OUT }, /* MMCCS0 */
|
|
{ 34, GPIO_CLR | GPIO_ALT_FN_2_OUT }, /* MMCCS0 */
|
|
{ 67, GPIO_CLR | GPIO_ALT_FN_1_OUT }, /* MMCCS0 */
|
|
|
|
{ 9, GPIO_CLR | GPIO_ALT_FN_1_OUT }, /* MMCCS1 */
|
|
{ 39, GPIO_CLR | GPIO_ALT_FN_1_OUT }, /* MMCCS1 */
|
|
{ 68, GPIO_CLR | GPIO_ALT_FN_1_OUT }, /* MMCCS1 */
|
|
#endif
|
|
|
|
{ -1 }
|
|
};
|
|
#endif
|
|
|
|
#if defined(CPU_XSCALE_PXA270)
|
|
/*
|
|
* Configurations of GPIO for PXA27x
|
|
*/
|
|
struct pxa2x0_gpioconf pxa27x_com_btuart_gpioconf[] = {
|
|
{ 42, GPIO_CLR | GPIO_ALT_FN_1_IN }, /* BTRXD */
|
|
{ 43, GPIO_CLR | GPIO_ALT_FN_2_OUT }, /* BTTXD */
|
|
|
|
#if 0 /* optional */
|
|
{ 44, GPIO_CLR | GPIO_ALT_FN_1_IN }, /* BTCTS */
|
|
{ 45, GPIO_CLR | GPIO_ALT_FN_2_OUT }, /* BTRTS */
|
|
#endif
|
|
|
|
{ -1 }
|
|
};
|
|
|
|
struct pxa2x0_gpioconf pxa27x_com_ffuart_gpioconf[] = {
|
|
#if 0 /* We can select and/or. */
|
|
{ 16, GPIO_CLR | GPIO_ALT_FN_3_OUT }, /* FFTXD */
|
|
{ 37, GPIO_CLR | GPIO_ALT_FN_3_OUT }, /* FFTXD */
|
|
{ 39, GPIO_CLR | GPIO_ALT_FN_2_OUT }, /* FFTXD */
|
|
{ 83, GPIO_CLR | GPIO_ALT_FN_2_OUT }, /* FFTXD */
|
|
{ 99, GPIO_CLR | GPIO_ALT_FN_3_OUT }, /* FFTXD */
|
|
|
|
{ 19, GPIO_CLR | GPIO_ALT_FN_3_IN }, /* FFRXD */
|
|
{ 33, GPIO_CLR | GPIO_ALT_FN_1_IN }, /* FFRXD */
|
|
{ 34, GPIO_CLR | GPIO_ALT_FN_1_IN }, /* FFRXD */
|
|
{ 41, GPIO_CLR | GPIO_ALT_FN_1_IN }, /* FFRXD */
|
|
{ 53, GPIO_CLR | GPIO_ALT_FN_1_IN }, /* FFRXD */
|
|
{ 85, GPIO_CLR | GPIO_ALT_FN_1_IN }, /* FFRXD */
|
|
{ 96, GPIO_CLR | GPIO_ALT_FN_3_IN }, /* FFRXD */
|
|
{ 102, GPIO_CLR | GPIO_ALT_FN_3_IN }, /* FFRXD */
|
|
|
|
{ 9, GPIO_CLR | GPIO_ALT_FN_3_IN }, /* FFCTS */
|
|
{ 26, GPIO_CLR | GPIO_ALT_FN_3_IN }, /* FFCTS */
|
|
{ 35, GPIO_CLR | GPIO_ALT_FN_1_IN }, /* FFCTS */
|
|
{ 100, GPIO_CLR | GPIO_ALT_FN_3_IN }, /* FFCTS */
|
|
|
|
{ 27, GPIO_CLR | GPIO_ALT_FN_3_OUT }, /* FFRTS */
|
|
{ 41, GPIO_CLR | GPIO_ALT_FN_2_OUT }, /* FFRTS */
|
|
{ 83, GPIO_CLR | GPIO_ALT_FN_3_OUT }, /* FFRTS */
|
|
{ 98, GPIO_CLR | GPIO_ALT_FN_3_OUT }, /* FFRTS */
|
|
|
|
{ 40, GPIO_CLR | GPIO_ALT_FN_2_OUT }, /* FFDTR */
|
|
{ 82, GPIO_CLR | GPIO_ALT_FN_3_OUT }, /* FFDTR */
|
|
|
|
{ 36, GPIO_CLR | GPIO_ALT_FN_1_IN }, /* FFDCD */
|
|
|
|
{ 33, GPIO_CLR | GPIO_ALT_FN_2_IN }, /* FFDSR */
|
|
{ 37, GPIO_CLR | GPIO_ALT_FN_1_IN }, /* FFDSR */
|
|
|
|
{ 38, GPIO_CLR | GPIO_ALT_FN_1_IN }, /* FFRI */
|
|
#endif
|
|
{ -1 }
|
|
};
|
|
|
|
struct pxa2x0_gpioconf pxa27x_com_stuart_gpioconf[] = {
|
|
{ 46, GPIO_CLR | GPIO_ALT_FN_2_IN }, /* STD_RXD */
|
|
{ 47, GPIO_CLR | GPIO_ALT_FN_1_OUT }, /* STD_TXD */
|
|
{ -1 }
|
|
};
|
|
|
|
struct pxa2x0_gpioconf pxa27x_i2c_gpioconf[] = {
|
|
{ 117, GPIO_CLR | GPIO_ALT_FN_1_IN }, /* SCL */
|
|
{ 118, GPIO_CLR | GPIO_ALT_FN_1_IN }, /* SDA */
|
|
{ -1 }
|
|
};
|
|
|
|
struct pxa2x0_gpioconf pxa27x_i2s_gpioconf[] = {
|
|
{ 28, GPIO_CLR | GPIO_ALT_FN_1_OUT }, /* I2S_BITCLK */
|
|
{ 29, GPIO_CLR | GPIO_ALT_FN_2_IN }, /* I2S_SDATA_IN */
|
|
{ 30, GPIO_CLR | GPIO_ALT_FN_1_OUT }, /* I2S_SDATA_OUT */
|
|
{ 31, GPIO_CLR | GPIO_ALT_FN_1_OUT }, /* I2S_SYNC */
|
|
{ 113, GPIO_CLR | GPIO_ALT_FN_1_OUT }, /* I2S_SYSCLK */
|
|
{ -1 }
|
|
};
|
|
|
|
struct pxa2x0_gpioconf pxa27x_ohci_gpioconf[] = {
|
|
#if 0 /* We can select and/or. */
|
|
{ 88, GPIO_CLR | GPIO_ALT_FN_1_IN }, /* USBHPWR1 */
|
|
{ 89, GPIO_CLR | GPIO_ALT_FN_2_OUT }, /* USBHPEN1 */
|
|
{ 119, GPIO_CLR | GPIO_ALT_FN_1_IN }, /* USBHPWR2 */
|
|
{ 120, GPIO_CLR | GPIO_ALT_FN_2_OUT }, /* USBHPEN2 */
|
|
#endif
|
|
{ -1 }
|
|
};
|
|
|
|
struct pxa2x0_gpioconf pxa27x_pcic_gpioconf[] = {
|
|
{ 48, GPIO_CLR | GPIO_ALT_FN_2_OUT }, /* nPOE */
|
|
{ 49, GPIO_CLR | GPIO_ALT_FN_2_OUT }, /* nPWE */
|
|
{ 50, GPIO_CLR | GPIO_ALT_FN_2_OUT }, /* nPIOR */
|
|
{ 51, GPIO_CLR | GPIO_ALT_FN_2_OUT }, /* nPIOW */
|
|
{ 55, GPIO_CLR | GPIO_ALT_FN_2_OUT }, /* nPREG */
|
|
{ 56, GPIO_CLR | GPIO_ALT_FN_1_IN }, /* nPWAIT */
|
|
{ 57, GPIO_CLR | GPIO_ALT_FN_1_IN }, /* nIOIS16 */
|
|
|
|
#if 0 /* We can select and/or. */
|
|
{ 85, GPIO_CLR | GPIO_ALT_FN_1_OUT }, /* nPCE1 */
|
|
{ 86, GPIO_CLR | GPIO_ALT_FN_1_OUT }, /* nPCE1 */
|
|
{ 102, GPIO_CLR | GPIO_ALT_FN_1_OUT }, /* nPCE1 */
|
|
|
|
{ 54, GPIO_CLR | GPIO_ALT_FN_2_OUT }, /* nPCE2 */
|
|
{ 78, GPIO_CLR | GPIO_ALT_FN_1_OUT }, /* nPCE2 */
|
|
{ 105, GPIO_CLR | GPIO_ALT_FN_1_OUT }, /* nPCE2 */
|
|
|
|
{ 79, GPIO_CLR | GPIO_ALT_FN_1_OUT }, /* pSKTSEL */
|
|
{ 104, GPIO_CLR | GPIO_ALT_FN_1_OUT }, /* pSKTSEL */
|
|
#endif
|
|
|
|
{ -1 }
|
|
};
|
|
|
|
struct pxa2x0_gpioconf pxa27x_pxaacu_gpioconf[] = {
|
|
{ 28, GPIO_CLR | GPIO_ALT_FN_1_IN }, /* BITCLK */
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{ 30, GPIO_CLR | GPIO_ALT_FN_2_OUT }, /* SDATA_OUT */
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|
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#if 0 /* We can select and/or. */
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{ 31, GPIO_CLR | GPIO_ALT_FN_2_OUT }, /* SYNC */
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{ 94, GPIO_CLR | GPIO_ALT_FN_1_OUT }, /* SYNC */
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|
|
|
{ 29, GPIO_CLR | GPIO_ALT_FN_1_IN }, /* SDATA_IN0 */
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{ 116, GPIO_CLR | GPIO_ALT_FN_2_IN }, /* SDATA_IN0 */
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|
|
|
{ 32, GPIO_CLR | GPIO_ALT_FN_1_IN }, /* SDATA_IN1 */
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|
{ 99, GPIO_CLR | GPIO_ALT_FN_2_IN }, /* SDATA_IN1 */
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|
|
|
{ 95, GPIO_CLR | GPIO_ALT_FN_1_OUT }, /* RESET_n */
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|
{ 113, GPIO_CLR | GPIO_ALT_FN_2_OUT }, /* RESET_n */
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#endif
|
|
|
|
{ -1 }
|
|
};
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|
|
|
struct pxa2x0_gpioconf pxa27x_pxamci_gpioconf[] = {
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|
{ 32, GPIO_CLR | GPIO_ALT_FN_2_OUT }, /* MMCLK */
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|
{ 92, GPIO_CLR | GPIO_ALT_FN_1_IN }, /* MMDAT<0> */
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|
{ 109, GPIO_CLR | GPIO_ALT_FN_1_IN }, /* MMDAT<1> */
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|
{ 110, GPIO_CLR | GPIO_ALT_FN_1_IN }, /* MMDAT<2>/MMCCS<0> */
|
|
{ 111, GPIO_CLR | GPIO_ALT_FN_1_IN }, /* MMDAT<3>/MMCCS<1> */
|
|
{ 112, GPIO_CLR | GPIO_ALT_FN_1_IN }, /* MMCMD */
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|
|
|
{ -1 }
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|
};
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|
#endif
|
|
|
|
void
|
|
pxa2x0_gpio_config(struct pxa2x0_gpioconf **conflist)
|
|
{
|
|
int i, j;
|
|
|
|
for (i = 0; conflist[i] != NULL; i++)
|
|
for (j = 0; conflist[i][j].pin != -1; j++)
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|
pxa2x0_gpio_set_function(conflist[i][j].pin,
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|
conflist[i][j].value);
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|
}
|