399 lines
8.6 KiB
C
399 lines
8.6 KiB
C
/* $NetBSD: becc_icu.c,v 1.12 2010/12/20 00:25:29 matt Exp $ */
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/*
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* Copyright (c) 2002 Wasabi Systems, Inc.
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* All rights reserved.
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*
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* Written by Jason R. Thorpe for Wasabi Systems, Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed for the NetBSD Project by
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* Wasabi Systems, Inc.
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* 4. The name of Wasabi Systems, Inc. may not be used to endorse
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* or promote products derived from this software without specific prior
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* written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Interrupt support for the ADI Engineering Big Endian Companion Chip.
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: becc_icu.c,v 1.12 2010/12/20 00:25:29 matt Exp $");
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#ifndef EVBARM_SPL_NOINLINE
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#define EVBARM_SPL_NOINLINE
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#endif
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/malloc.h>
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#include <sys/bus.h>
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#include <sys/intr.h>
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#include <uvm/uvm_extern.h>
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#include <arm/cpufunc.h>
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#include <arm/xscale/beccreg.h>
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#include <arm/xscale/beccvar.h>
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#include <arm/xscale/i80200reg.h>
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#include <arm/xscale/i80200var.h>
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/* Interrupt handler queues. */
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struct intrq intrq[NIRQ];
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/* Interrupts to mask at each level. */
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uint32_t becc_imask[NIPL];
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/* Interrupts pending. */
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volatile uint32_t becc_ipending;
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volatile uint32_t becc_sipending;
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/* Software copy of the IRQs we have enabled. */
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volatile uint32_t intr_enabled;
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/* Mask if interrupts steered to FIQs. */
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uint32_t intr_steer;
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/*
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* Interrupt bit names.
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* XXX Some of these are BRH-centric.
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*/
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const char * const becc_irqnames[] = {
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"soft",
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"timer A",
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"timer B",
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"irq 3",
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"irq 4",
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"irq 5",
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"irq 6",
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"diagerr",
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"DMA EOT",
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"DMA PERR",
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"DMA TABT",
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"DMA MABT",
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"irq 12",
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"irq 13",
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"irq 14",
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"irq 15",
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"PCI PERR",
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"irq 17",
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"irq 18",
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"PCI SERR",
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"PCI OAPE",
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"PCI OATA",
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"PCI OAMA",
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"irq 23",
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"irq 24",
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"irq 25",
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"irq 26", /* PCI INTA */
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"irq 27", /* PCI INTB */
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"irq 28", /* PCI INTC */
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"irq 29", /* PCI INTD */
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"pushbutton",
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"irq 31",
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};
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void becc_intr_dispatch(struct irqframe *frame);
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static inline uint32_t
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becc_icsr_read(void)
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{
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uint32_t icsr;
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icsr = BECC_CSR_READ(BECC_ICSR);
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/*
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* The ICSR register shows bits that are active even if they are
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* masked in ICMR, so we have to mask them off with the interrupts
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* we consider enabled.
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*/
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return (icsr & intr_enabled);
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}
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static inline void
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becc_set_intrsteer(void)
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{
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BECC_CSR_WRITE(BECC_ICSTR, intr_steer & ICU_VALID_MASK);
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(void) BECC_CSR_READ(BECC_ICSTR);
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}
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static inline void
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becc_enable_irq(int irq)
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{
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intr_enabled |= (1U << irq);
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becc_set_intrmask();
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}
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static inline void
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becc_disable_irq(int irq)
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{
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intr_enabled &= ~(1U << irq);
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becc_set_intrmask();
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}
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/*
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* NOTE: This routine must be called with interrupts disabled in the CPSR.
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*/
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static void
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becc_intr_calculate_masks(void)
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{
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struct intrq *iq;
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struct intrhand *ih;
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int irq, ipl;
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/* First, figure out which IPLs each IRQ has. */
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for (irq = 0; irq < NIRQ; irq++) {
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int levels = 0;
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iq = &intrq[irq];
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becc_disable_irq(irq);
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for (ih = TAILQ_FIRST(&iq->iq_list); ih != NULL;
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ih = TAILQ_NEXT(ih, ih_list))
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levels |= (1U << ih->ih_ipl);
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iq->iq_levels = levels;
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}
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/* Next, figure out which IRQs are used by each IPL. */
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for (ipl = 0; ipl < NIPL; ipl++) {
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int irqs = 0;
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for (irq = 0; irq < NIRQ; irq++) {
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if (intrq[irq].iq_levels & (1U << ipl))
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irqs |= (1U << irq);
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}
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becc_imask[ipl] = irqs;
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}
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becc_imask[IPL_NONE] = 0;
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/*
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* Enforce a hierarchy that gives "slow" device (or devices with
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* limited input buffer space/"real-time" requirements) a better
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* chance at not dropping data.
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*/
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becc_imask[IPL_VM] |= becc_imask[IPL_SOFTSERIAL];
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becc_imask[IPL_SCHED] |= becc_imask[IPL_VM];
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becc_imask[IPL_HIGH] |= becc_imask[IPL_SCHED];
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/*
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* Now compute which IRQs must be blocked when servicing any
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* given IRQ.
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*/
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for (irq = 0; irq < NIRQ; irq++) {
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int irqs = (1U << irq);
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iq = &intrq[irq];
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if (TAILQ_FIRST(&iq->iq_list) != NULL)
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becc_enable_irq(irq);
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for (ih = TAILQ_FIRST(&iq->iq_list); ih != NULL;
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ih = TAILQ_NEXT(ih, ih_list))
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irqs |= becc_imask[ih->ih_ipl];
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iq->iq_mask = irqs;
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}
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}
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void
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splx(int new)
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{
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becc_splx(new);
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}
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int
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_spllower(int ipl)
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{
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return (becc_spllower(ipl));
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}
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int
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_splraise(int ipl)
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{
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return (becc_splraise(ipl));
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}
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/*
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* becc_icu_init:
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*
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* Initialize the BECC ICU. Called early in bootstrap
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* to make sure the ICU is in a pristine state.
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*/
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void
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becc_icu_init(void)
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{
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intr_enabled = 0; /* All interrupts disabled */
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becc_set_intrmask();
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intr_steer = 0; /* All interrupts steered to IRQ */
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becc_set_intrsteer();
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i80200_extirq_dispatch = becc_intr_dispatch;
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i80200_intr_enable(INTCTL_IM);
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}
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/*
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* becc_intr_init:
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*
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* Initialize the rest of the interrupt subsystem, making it
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* ready to handle interrupts from devices.
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*/
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void
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becc_intr_init(void)
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{
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struct intrq *iq;
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int i;
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intr_enabled = 0;
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for (i = 0; i < NIRQ; i++) {
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iq = &intrq[i];
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TAILQ_INIT(&iq->iq_list);
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evcnt_attach_dynamic(&iq->iq_ev, EVCNT_TYPE_INTR,
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NULL, "becc", becc_irqnames[i]);
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}
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becc_intr_calculate_masks();
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/* Enable IRQs (don't yet use FIQs). */
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enable_interrupts(I32_bit);
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}
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void *
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becc_intr_establish(int irq, int ipl, int (*func)(void *), void *arg)
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{
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struct intrq *iq;
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struct intrhand *ih;
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uint32_t oldirqstate;
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if (irq < 0 || irq > NIRQ)
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panic("becc_intr_establish: IRQ %d out of range", irq);
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ih = malloc(sizeof(*ih), M_DEVBUF, M_NOWAIT);
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if (ih == NULL)
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return (NULL);
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ih->ih_func = func;
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ih->ih_arg = arg;
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ih->ih_ipl = ipl;
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ih->ih_irq = irq;
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iq = &intrq[irq];
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/* All BECC interrupts are level-triggered. */
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iq->iq_ist = IST_LEVEL;
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oldirqstate = disable_interrupts(I32_bit);
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TAILQ_INSERT_TAIL(&iq->iq_list, ih, ih_list);
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becc_intr_calculate_masks();
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restore_interrupts(oldirqstate);
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return (ih);
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}
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void
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becc_intr_disestablish(void *cookie)
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{
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struct intrhand *ih = cookie;
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struct intrq *iq = &intrq[ih->ih_irq];
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uint32_t oldirqstate;
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oldirqstate = disable_interrupts(I32_bit);
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TAILQ_REMOVE(&iq->iq_list, ih, ih_list);
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becc_intr_calculate_masks();
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restore_interrupts(oldirqstate);
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}
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void
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becc_intr_dispatch(struct irqframe *frame)
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{
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struct intrq *iq;
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struct intrhand *ih;
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uint32_t oldirqstate, irq, ibit, hwpend;
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struct cpu_info * const ci = curcpu();
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const int ppl = ci->ci_cpl;
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const uint32_t imask = becc_imask[ppl];
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hwpend = becc_icsr_read();
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/*
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* Disable all the interrupts that are pending. We will
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* reenable them once they are processed and not masked.
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*/
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intr_enabled &= ~hwpend;
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becc_set_intrmask();
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while (hwpend != 0) {
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irq = ffs(hwpend) - 1;
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ibit = (1U << irq);
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hwpend &= ~ibit;
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if (imask & ibit) {
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/*
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* IRQ is masked; mark it as pending and check
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* the next one. Note: the IRQ is already disabled.
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*/
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becc_ipending |= ibit;
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continue;
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}
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becc_ipending &= ~ibit;
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iq = &intrq[irq];
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iq->iq_ev.ev_count++;
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ci->ci_data.cpu_nintr++;
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TAILQ_FOREACH(ih, &iq->iq_list, ih_list) {
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ci->ci_cpl = ih->ih_ipl;
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oldirqstate = enable_interrupts(I32_bit);
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(void) (*ih->ih_func)(ih->ih_arg ? ih->ih_arg : frame);
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restore_interrupts(oldirqstate);
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}
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ci->ci_cpl = ppl;
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/* Re-enable this interrupt now that's it's cleared. */
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intr_enabled |= ibit;
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becc_set_intrmask();
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}
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if (becc_ipending & ~imask) {
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intr_enabled |= (becc_ipending & ~imask);
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becc_set_intrmask();
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}
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#ifdef __HAVE_FAST_SOFTINTS
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cpu_dosoftints();
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#endif
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}
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