78 lines
3.7 KiB
C
78 lines
3.7 KiB
C
/* $NetBSD: epsmcreg.h,v 1.1 2005/11/12 05:33:23 hamajima Exp $ */
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/*
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* Copyright (c) 2005 HAMAJIMA Katsuomi. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/* Cirrus Logic EP9315
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Static Memory Controller register
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http://www.cirrus.com/jp/pubs/manual/EP9315_Users_Guide.pdf */
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#ifndef _EPSMCREG_H_
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#define _EPSMCREG_H_
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#define EP93XX_SMC_BCR0 0x00 /* Bank0 Configuration Register (R/W) */
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#define EP93XX_SMC_BCR1 0x04 /* Bank1 Configuration Register (R/W) */
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#define EP93XX_SMC_BCR2 0x08 /* Bank2 Configuration Register (R/W) */
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#define EP93XX_SMC_BCR3 0x0c /* Bank3 Configuration Register (R/W) */
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#define EP93XX_SMC_BCR6 0x18 /* Bank6 Configuration Register (R/W) */
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#define EP93XX_SMC_BCR7 0x1c /* Bank7 Configuration Register (R/W) */
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#define EP93XX_SMC_IDCY_MASK 0x0000000f /* Idle Cycle */
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#define EP93XX_SMC_IDCY_SHIFT 0
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#define EP93XX_SMC_WST1_MASK 0x000003e0 /* Wait State 1 */
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#define EP93XX_SMC_WST1_SHIFT 5
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#define EP93XX_SMC_RBLE (1<<10) /* Read Byte Lane Enable */
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#define EP93XX_SMC_WST2_MASK 0x0000f800 /* Wait State 2 */
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#define EP93XX_SMC_WST2_SHIFT 11
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#define EP93XX_SMC_WPERR (1<<25) /* Write Protect Error status */
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#define EP93XX_SMC_WP (1<<26) /* Write Protect */
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#define EP93XX_SMC_PME (1<<27) /* Page Mode Enable */
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#define EP93XX_SMC_MW_MASK 0x30000000 /* Memory Width */
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#define EP93XX_SMC_MW_SHIFT 28
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#define EP93XX_SMC_EBIBRKDIS (1<<30) /* EBI Break Disable */
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#define EP93XX_PCMCIA0_Attribute 0x20 /* PCMCIA Attribute (R/W) */
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#define EP93XX_PCMCIA0_Common 0x24 /* PCMCIA Common (R/W) */
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#define EP93XX_PCMCIA0_IO 0x28 /* PCMCIA IO (R/W) */
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#define EP93XX_PCMCIA1_Attribute 0x30 /* PCMCIA Attribute (R/W) */
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#define EP93XX_PCMCIA1_Common 0x34 /* PCMCIA Common (R/W) */
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#define EP93XX_PCMCIA1_IO 0x38 /* PCMCIA IO (R/W) */
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#define EP93XX_PCMCIA_WIDTH_16 (1<<31) /* width */
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#define EP93XX_PCMCIA_ACCESS_MASK 0x00ff0000 /* access time */
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#define EP93XX_PCMCIA_ACCESS_SHIFT 16
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#define EP93XX_PCMCIA_HOLD_MASK 0x00000f00 /* Hole time */
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#define EP93XX_PCMCIA_HOLD_SHIFT 8
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#define EP93XX_PCMCIA_PRECHARGE_MASK 0x000000ff /* pre-charge delay */
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#define EP93XX_PCMCIA_PRECHARGE_SHIFT 0
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#define EP93XX_PCMCIA_Ctrl 0x40 /* PCMCIA Control */
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#define EP93XX_PCMCIA_WEN (1<<4) /* External wait state */
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#define EP93XX_PCMCIA_RST (1<<2) /* Reset PC card */
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#define EP93XX_PCMCIA_EN_DISABLE 0x0 /* PC card disabled */
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#define EP93XX_PCMCIA_EN_CF 0x1 /* CF mode */
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#define EP93XX_PCMCIA_EN_PCMCIA 0x2 /* PCMCIA mode */
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#define EP93XX_PCMCIA_EN_MASK 0x3
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#endif /* _EPSMCREG_H_ */
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