137 lines
5.2 KiB
C
137 lines
5.2 KiB
C
/* $NetBSD: epgpioreg.h,v 1.1 2005/11/12 05:33:23 hamajima Exp $ */
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/*
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* Copyright (c) 2005 HAMAJIMA Katsuomi. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/* Cirrus Logic EP9315
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GPIO Interface register
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http://www.cirrus.com/jp/pubs/manual/EP9315_Users_Guide.pdf */
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#ifndef _EPGPIOREG_H_
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#define _EPGPIOREG_H_
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/* Port A
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7:0 EGPIO[7:0]
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6 I2S port 2 SDO2
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5 I2S port 1 SDI1
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4 I2S port 1 SDO1
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3 HDLC clock or TENn
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2 DMARQ
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1 RTC 32.768kHz reference clock
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0 Modem Ring Indicator */
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#define EP93XX_GPIO_PADR 0x00 /* Data (R/W) */
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#define EP93XX_GPIO_PADDR 0x10 /* Data Direction (R/W) */
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#define EP93XX_GPIO_AIntEn 0x9c /* Interrupt Enable (R/W) */
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#define EP93XX_GPIO_AIntType1 0x90 /* Interrupt edge or level (R/W) */
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#define EP93XX_GPIO_AIntType2 0x94 /* rising/falling edge, high/low level (R/W) */
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#define EP93XX_GPIO_AEOI 0x98 /* clear interrupt (W) */
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#define EP93XX_GPIO_ADB 0xa8 /* Interrupt debounce enable (R/W) */
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#define EP93XX_GPIO_RawIntStsA 0xa4 /* Raw Interrupt Status (R) */
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#define EP93XX_GPIO_IntStsA 0xa0 /* Masked interrupt Status (R) */
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/* Port B
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7:0 EGPIO[15:8]
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7 DASPn
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5 I2S port 2 SDI2 */
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#define EP93XX_GPIO_PBDR 0x04 /* Data (R/W) */
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#define EP93XX_GPIO_PBDDR 0x14 /* Data Direction (R/W) */
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#define EP93XX_GPIO_BIntEn 0xb8 /* Interrupt Enable (R/W) */
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#define EP93XX_GPIO_BIntType1 0xac /* Interrupt edge or level (R/W) */
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#define EP93XX_GPIO_BIntType2 0xb0 /* rising/falling edge, high/low level (R/W) */
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#define EP93XX_GPIO_BEOI 0xb4 /* clear interrupt (W) */
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#define EP93XX_GPIO_BDB 0xc4 /* Interrupt debounce enable (R/W) */
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#define EP93XX_GPIO_RawIntStsB 0xc0 /* Raw Interrupt Status (R) */
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#define EP93XX_GPIO_IntStsB 0xbc /* Masked interrupt Status (R) */
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/* Port C
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7:0 ROW[7:0] Key Matrix row pin */
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#define EP93XX_GPIO_PCDR 0x08 /* Data (R/W) */
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#define EP93XX_GPIO_PCDDR 0x18 /* Data Direction (R/W) */
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/* Port D
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7:0 COL[7:0] Key Matrix column pin */
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#define EP93XX_GPIO_PDDR 0x0c /* Data (R/W) */
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#define EP93XX_GPIO_PDDDR 0x1c /* Data Direction (R/W) */
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/* Port E
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7:5 IDEDA[2:0] IDE control pin
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4 IDECS1n IDE control pin
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3 IDECS0n IDE control pin
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2 DIORn IDE control pin
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1 RDLED Red LED pin
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0 GRLED Green LED pin */
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#define EP93XX_GPIO_PEDR 0x20 /* Data (R/W) */
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#define EP93XX_GPIO_PEDDR 0x24 /* Data Direction (R/W) */
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/* Port F
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7 VS2 PCMCIA pin
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6 READY PCMCIA pin
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5 VS1 PCMCIA pin
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4 MCBVD2 PCMCIA pin
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3 MCBVD1 PCMCIA pin
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2 MCCD2 PCMCIA pin
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1 MCCD1 PCMCIA pin
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0 WP PCMCIA pin */
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#define EP93XX_GPIO_PFDR 0x30 /* Data (R/W) */
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#define EP93XX_GPIO_PFDDR 0x34 /* Data Direction (R/W) */
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#define EP93XX_GPIO_FIntEn 0x58 /* Interrupt Enable (R/W) */
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#define EP93XX_GPIO_FIntType1 0x4c /* Interrupt edge or level (R/W) */
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#define EP93XX_GPIO_FIntType2 0x50 /* rising/falling edge, high/low level (R/W) */
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#define EP93XX_GPIO_FEOI 0x54 /* clear interrupt (W) */
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#define EP93XX_GPIO_FDB 0x64 /* Interrupt debounce enable (R/W) */
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#define EP93XX_GPIO_RawIntStsF 0x60 /* Raw Interrupt Status (R) */
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#define EP93XX_GPIO_IntStsF 0x5c /* Masked interrupt Status (R) */
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/* Port G
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7:4 DD[15:12] IDE data pin
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3:2 SLA[1:0] PCMCIA voltage control pin
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1 EEDAT EEPROM data pin
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0 EECLK EEPROM clock pin */
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#define EP93XX_GPIO_PGDR 0x38 /* Data (R/W) */
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#define EP93XX_GPIO_PGDDR 0x3c /* Data Direction (R/W) */
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/* Port H
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7:0 DD[7:0] IDE data pin */
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#define EP93XX_GPIO_PHDR 0x40 /* Data (R/W) */
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#define EP93XX_GPIO_PHDDR 0x44 /* Data Direction (R/W) */
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/* EEPROM interface pin drive type (R/W) */
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#define EP93XX_GPIO_EEDrive 0xc8
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#define EP93XX_GPIO_DATOD (1<<1) /* EEDAT pin */
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#define EP93XX_GPIO_CLKOD (1<<0) /* EECLK pin */
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/* Interrupt */
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#define EP93XX_GPIO0_INTR 19 /* Port F bit 0 */
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#define EP93XX_GPIO1_INTR 20 /* Port F bit 1 */
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#define EP93XX_GPIO2_INTR 21 /* Port F bit 2 */
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#define EP93XX_GPIO3_INTR 22 /* Port F bit 3 */
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#define EP93XX_GPIO4_INTR 47 /* Port F bit 4 */
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#define EP93XX_GPIO5_INTR 48 /* Port F bit 5 */
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#define EP93XX_GPIO6_INTR 49 /* Port F bit 6 */
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#define EP93XX_GPIO7_INTR 50 /* Port F bit 7 */
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#define EP93XX_GPIO_INTR 59 /* Port A or B */
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#endif /* _EPGPIOREG_H_ */
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