659 lines
18 KiB
C
659 lines
18 KiB
C
/* $NetBSD: flsc.c,v 1.33 2004/02/13 11:36:10 wiz Exp $ */
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/*
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* Copyright (c) 1997 Michael L. Hitch
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* Copyright (c) 1995 Daniel Widenfalk
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* Copyright (c) 1994 Christian E. Hopps
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* Copyright (c) 1982, 1990 The Regents of the University of California.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Daniel Widenfalk
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* and Michael L. Hitch.
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* 4. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/*
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* Initial amiga Fastlane driver by Daniel Widenfalk. Conversion to
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* 53c9x MI driver by Michael L. Hitch (mhitch@montana.edu).
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*/
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#include "opt_ddb.h"
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: flsc.c,v 1.33 2004/02/13 11:36:10 wiz Exp $");
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#include <sys/types.h>
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#include <sys/errno.h>
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#include <sys/ioctl.h>
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#include <sys/device.h>
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#include <sys/buf.h>
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#include <sys/proc.h>
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#include <sys/user.h>
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#include <sys/queue.h>
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#include <uvm/uvm_extern.h>
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#include <dev/scsipi/scsi_all.h>
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#include <dev/scsipi/scsipi_all.h>
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#include <dev/scsipi/scsiconf.h>
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#include <dev/scsipi/scsi_message.h>
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#include <machine/cpu.h>
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#include <machine/param.h>
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#include <dev/ic/ncr53c9xreg.h>
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#include <dev/ic/ncr53c9xvar.h>
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#include <amiga/amiga/isr.h>
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#include <amiga/dev/flscvar.h>
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#include <amiga/dev/zbusvar.h>
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void flscattach(struct device *, struct device *, void *);
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int flscmatch(struct device *, struct cfdata *, void *);
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/* Linkup to the rest of the kernel */
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CFATTACH_DECL(flsc, sizeof(struct flsc_softc),
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flscmatch, flscattach, NULL, NULL);
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/*
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* Functions and the switch for the MI code.
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*/
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u_char flsc_read_reg(struct ncr53c9x_softc *, int);
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void flsc_write_reg(struct ncr53c9x_softc *, int, u_char);
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int flsc_dma_isintr(struct ncr53c9x_softc *);
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void flsc_dma_reset(struct ncr53c9x_softc *);
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int flsc_dma_intr(struct ncr53c9x_softc *);
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int flsc_dma_setup(struct ncr53c9x_softc *, caddr_t *,
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size_t *, int, size_t *);
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void flsc_dma_go(struct ncr53c9x_softc *);
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void flsc_dma_stop(struct ncr53c9x_softc *);
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int flsc_dma_isactive(struct ncr53c9x_softc *);
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void flsc_clear_latched_intr(struct ncr53c9x_softc *);
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struct ncr53c9x_glue flsc_glue = {
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flsc_read_reg,
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flsc_write_reg,
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flsc_dma_isintr,
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flsc_dma_reset,
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flsc_dma_intr,
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flsc_dma_setup,
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flsc_dma_go,
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flsc_dma_stop,
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flsc_dma_isactive,
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flsc_clear_latched_intr,
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};
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/* Maximum DMA transfer length to reduce impact on high-speed serial input */
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u_long flsc_max_dma = 1024;
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extern int ser_open_speed;
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extern int ncr53c9x_debug;
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extern u_long scsi_nosync;
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extern int shift_nosync;
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/*
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* if we are an Advanced Systems & Software FastlaneZ3
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*/
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int
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flscmatch(struct device *parent, struct cfdata *cf, void *aux)
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{
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struct zbus_args *zap;
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if (!is_a4000() && !is_a3000())
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return(0);
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zap = aux;
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if (zap->manid == 0x2140 && zap->prodid == 11
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&& iszthreepa(zap->pa))
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return(1);
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return(0);
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}
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/*
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* Attach this instance, and then all the sub-devices
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*/
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void
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flscattach(struct device *parent, struct device *self, void *aux)
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{
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struct flsc_softc *fsc = (void *)self;
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struct ncr53c9x_softc *sc = &fsc->sc_ncr53c9x;
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struct zbus_args *zap;
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/*
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* Set up the glue for MI code early; we use some of it here.
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*/
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sc->sc_glue = &flsc_glue;
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/*
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* Save the regs
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*/
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zap = aux;
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fsc->sc_dmabase = (volatile u_char *)zap->va;
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fsc->sc_reg = &((volatile u_char *)zap->va)[0x1000001];
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sc->sc_freq = 40; /* Clocked at 40Mhz */
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printf(": address %p", fsc->sc_reg);
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sc->sc_id = 7;
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/*
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* It is necessary to try to load the 2nd config register here,
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* to find out what rev the flsc chip is, else the flsc_reset
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* will not set up the defaults correctly.
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*/
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sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB;
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sc->sc_cfg2 = NCRCFG2_SCSI2 | NCRCFG2_FE;
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sc->sc_cfg3 = 0x08 /*FCLK*/ | NCRESPCFG3_FSCSI | NCRESPCFG3_CDB;
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sc->sc_rev = NCR_VARIANT_FAS216;
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/*
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* This is the value used to start sync negotiations
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* Note that the NCR register "SYNCTP" is programmed
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* in "clocks per byte", and has a minimum value of 4.
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* The SCSI period used in negotiation is one-fourth
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* of the time (in nanoseconds) needed to transfer one byte.
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* Since the chip's clock is given in MHz, we have the following
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* formula: 4 * period = (1000 / freq) * 4
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*/
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sc->sc_minsync = 1000 / sc->sc_freq;
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if (((scsi_nosync >> shift_nosync) & 0xff00) == 0xff00)
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sc->sc_minsync = 0;
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/* Really no limit, but since we want to fit into the TCR... */
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sc->sc_maxxfer = 64 * 1024;
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fsc->sc_portbits = 0xa0 | FLSC_PB_EDI | FLSC_PB_ESI;
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fsc->sc_hardbits = fsc->sc_reg[0x40];
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fsc->sc_alignbuf = (char *)((u_long)fsc->sc_unalignbuf & -4);
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sc->sc_dev.dv_cfdata->cf_flags |= (scsi_nosync >> shift_nosync) & 0xffff;
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shift_nosync += 16;
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ncr53c9x_debug |= (scsi_nosync >> shift_nosync) & 0xffff;
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shift_nosync += 16;
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/*
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* Configure interrupts.
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*/
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fsc->sc_isr.isr_intr = ncr53c9x_intr;
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fsc->sc_isr.isr_arg = sc;
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fsc->sc_isr.isr_ipl = 2;
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add_isr(&fsc->sc_isr);
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fsc->sc_reg[0x40] = fsc->sc_portbits;
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/*
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* Now try to attach all the sub-devices
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*/
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sc->sc_adapter.adapt_request = ncr53c9x_scsipi_request;
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sc->sc_adapter.adapt_minphys = minphys;
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ncr53c9x_attach(sc);
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}
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/*
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* Glue functions.
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*/
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u_char
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flsc_read_reg(struct ncr53c9x_softc *sc, int reg)
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{
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struct flsc_softc *fsc = (struct flsc_softc *)sc;
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return fsc->sc_reg[reg * 4];
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}
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void
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flsc_write_reg(struct ncr53c9x_softc *sc, int reg, u_char val)
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{
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struct flsc_softc *fsc = (struct flsc_softc *)sc;
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struct ncr53c9x_tinfo *ti;
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u_char v = val;
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if (fsc->sc_piomode && reg == NCR_CMD &&
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v == (NCRCMD_TRANS|NCRCMD_DMA)) {
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v = NCRCMD_TRANS;
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}
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/*
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* Can't do synchronous transfers in XS_CTL_POLL mode:
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* If starting XS_CTL_POLL command, clear defer sync negotiation
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* by clearing the T_NEGOTIATE flag. If starting XS_CTL_POLL and
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* the device is currently running synchronous, force another
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* T_NEGOTIATE with 0 offset.
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*/
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if (reg == NCR_SELID) {
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ti = &sc->sc_tinfo[
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sc->sc_nexus->xs->xs_periph->periph_target];
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if (sc->sc_nexus->xs->xs_control & XS_CTL_POLL) {
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if (ti->flags & T_SYNCMODE) {
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ti->flags ^= T_SYNCMODE | T_NEGOTIATE;
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} else if (ti->flags & T_NEGOTIATE) {
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ti->flags ^= T_NEGOTIATE | T_SYNCHOFF;
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/* save T_NEGOTIATE in private flags? */
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}
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} else {
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/*
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* If we haven't attempted sync negotiation yet,
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* do it now.
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*/
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if ((ti->flags & (T_SYNCMODE | T_SYNCHOFF)) ==
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T_SYNCHOFF &&
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sc->sc_minsync != 0) /* XXX */
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ti->flags ^= T_NEGOTIATE | T_SYNCHOFF;
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}
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}
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if (reg == NCR_CMD && v == NCRCMD_SETATN &&
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sc->sc_flags & NCR_SYNCHNEGO &&
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sc->sc_nexus->xs->xs_control & XS_CTL_POLL) {
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ti = &sc->sc_tinfo[
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sc->sc_nexus->xs->xs_periph->periph_target];
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ti->offset = 0;
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}
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fsc->sc_reg[reg * 4] = v;
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}
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int
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flsc_dma_isintr(struct ncr53c9x_softc *sc)
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{
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struct flsc_softc *fsc = (struct flsc_softc *)sc;
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unsigned hardbits;
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hardbits = fsc->sc_reg[0x40];
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if (hardbits & FLSC_HB_IACT)
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return (fsc->sc_csr = 0);
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if (sc->sc_state == NCR_CONNECTED || sc->sc_state == NCR_SELECTING)
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fsc->sc_portbits |= FLSC_PB_LED;
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else
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fsc->sc_portbits &= ~FLSC_PB_LED;
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if ((hardbits & FLSC_HB_CREQ) && !(hardbits & FLSC_HB_MINT) &&
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fsc->sc_reg[NCR_STAT * 4] & NCRSTAT_INT) {
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return 1;
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}
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/* Do I still need this? */
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if (fsc->sc_piomode && fsc->sc_reg[NCR_STAT * 4] & NCRSTAT_INT &&
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!(hardbits & FLSC_HB_MINT))
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return 1;
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fsc->sc_reg[0x40] = fsc->sc_portbits & ~FLSC_PB_INT_BITS;
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fsc->sc_reg[0x40] = fsc->sc_portbits;
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return 0;
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}
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void
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flsc_clear_latched_intr(struct ncr53c9x_softc *sc)
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{
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struct flsc_softc *fsc = (struct flsc_softc *)sc;
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fsc->sc_reg[0x40] = fsc->sc_portbits & ~FLSC_PB_INT_BITS;
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fsc->sc_reg[0x40] = fsc->sc_portbits;
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}
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void
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flsc_dma_reset(struct ncr53c9x_softc *sc)
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{
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struct flsc_softc *fsc = (struct flsc_softc *)sc;
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struct ncr53c9x_tinfo *ti;
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if (sc->sc_nexus)
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ti = &sc->sc_tinfo[sc->sc_nexus->xs->xs_periph->periph_target];
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else
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ti = &sc->sc_tinfo[1]; /* XXX */
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if (fsc->sc_active) {
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printf("dmaaddr %p dmasize %d stat %x flags %x off %d per %d ff %x",
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*fsc->sc_dmaaddr, fsc->sc_dmasize, fsc->sc_reg[NCR_STAT * 4],
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ti->flags, ti->offset, ti->period, fsc->sc_reg[NCR_FFLAG * 4]);
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printf(" intr %x\n", fsc->sc_reg[NCR_INTR * 4]);
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#ifdef DDB
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Debugger();
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#endif
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}
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fsc->sc_portbits &= ~FLSC_PB_DMA_BITS;
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fsc->sc_reg[0x40] = fsc->sc_portbits;
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fsc->sc_reg[0x80] = 0;
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*((u_long *)fsc->sc_dmabase) = 0;
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fsc->sc_active = 0;
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fsc->sc_piomode = 0;
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}
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int
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flsc_dma_intr(struct ncr53c9x_softc *sc)
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{
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register struct flsc_softc *fsc = (struct flsc_softc *)sc;
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register u_char *p;
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volatile u_char *cmdreg, *intrreg, *statreg, *fiforeg;
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register u_int flscphase, flscstat, flscintr;
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register int cnt;
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NCR_DMA(("flsc_dma_intr: pio %d cnt %d int %x stat %x fifo %d ",
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fsc->sc_piomode, fsc->sc_dmasize, sc->sc_espintr, sc->sc_espstat,
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fsc->sc_reg[NCR_FFLAG * 4] & NCRFIFO_FF));
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if (!(fsc->sc_reg[0x40] & FLSC_HB_CREQ))
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printf("flsc_dma_intr: csr %x stat %x intr %x\n", fsc->sc_csr,
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sc->sc_espstat, sc->sc_espintr);
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if (fsc->sc_active == 0) {
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printf("flsc_intr--inactive DMA\n");
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return -1;
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}
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/* if DMA transfer, update sc_dmaaddr and sc_pdmalen, else PIO xfer */
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if (fsc->sc_piomode == 0) {
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fsc->sc_portbits &= ~FLSC_PB_DMA_BITS;
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fsc->sc_reg[0x40] = fsc->sc_portbits;
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fsc->sc_reg[0x80] = 0;
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*((u_long *)fsc->sc_dmabase) = 0;
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cnt = fsc->sc_reg[NCR_TCL * 4];
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cnt += fsc->sc_reg[NCR_TCM * 4] << 8;
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cnt += fsc->sc_reg[NCR_TCH * 4] << 16;
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if (!fsc->sc_datain) {
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cnt += fsc->sc_reg[NCR_FFLAG * 4] & NCRFIFO_FF;
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fsc->sc_reg[NCR_CMD * 4] = NCRCMD_FLUSH;
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}
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cnt = fsc->sc_dmasize - cnt; /* number of bytes transferred */
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NCR_DMA(("DMA xferred %d\n", cnt));
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if (fsc->sc_xfr_align) {
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int i;
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for (i = 0; i < cnt; ++i)
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(*fsc->sc_dmaaddr)[i] = fsc->sc_alignbuf[i];
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fsc->sc_xfr_align = 0;
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}
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*fsc->sc_dmaaddr += cnt;
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*fsc->sc_pdmalen -= cnt;
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fsc->sc_active = 0;
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return 0;
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}
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if ((sc->sc_espintr & NCRINTR_BS) == 0) {
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fsc->sc_active = 0;
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fsc->sc_piomode = 0;
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NCR_DMA(("no NCRINTR_BS\n"));
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return 0;
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}
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cnt = fsc->sc_dmasize;
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#if 0
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if (cnt == 0) {
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printf("data interrupt, but no count left.");
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}
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#endif
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p = *fsc->sc_dmaaddr;
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flscphase = sc->sc_phase;
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flscstat = (u_int) sc->sc_espstat;
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flscintr = (u_int) sc->sc_espintr;
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cmdreg = fsc->sc_reg + NCR_CMD * 4;
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fiforeg = fsc->sc_reg + NCR_FIFO * 4;
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statreg = fsc->sc_reg + NCR_STAT * 4;
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intrreg = fsc->sc_reg + NCR_INTR * 4;
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NCR_DMA(("PIO %d datain %d phase %d stat %x intr %x\n",
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cnt, fsc->sc_datain, flscphase, flscstat, flscintr));
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do {
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if (fsc->sc_datain) {
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*p++ = *fiforeg;
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cnt--;
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if (flscphase == DATA_IN_PHASE) {
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*cmdreg = NCRCMD_TRANS;
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} else {
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fsc->sc_active = 0;
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}
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} else {
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NCR_DMA(("flsc_dma_intr: PIO out- phase %d cnt %d active %d\n", flscphase, cnt,
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fsc->sc_active));
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if ( (flscphase == DATA_OUT_PHASE)
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|| (flscphase == MESSAGE_OUT_PHASE)) {
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int n;
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n = 16 - (fsc->sc_reg[NCR_FFLAG * 4] & NCRFIFO_FF);
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if (n > cnt)
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n = cnt;
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cnt -= n;
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while (n-- > 0)
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*fiforeg = *p++;
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*cmdreg = NCRCMD_TRANS;
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} else {
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fsc->sc_active = 0;
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}
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}
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if (fsc->sc_active && cnt) {
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while (!(*statreg & 0x80));
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flscstat = *statreg;
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flscintr = *intrreg;
|
|
flscphase = (flscintr & NCRINTR_DIS)
|
|
? /* Disconnected */ BUSFREE_PHASE
|
|
: flscstat & PHASE_MASK;
|
|
}
|
|
} while (cnt && fsc->sc_active && (flscintr & NCRINTR_BS));
|
|
#if 1
|
|
if (fsc->sc_dmasize < 8 && cnt)
|
|
printf("flsc_dma_intr: short transfer: dmasize %d cnt %d\n",
|
|
fsc->sc_dmasize, cnt);
|
|
#endif
|
|
NCR_DMA(("flsc_dma_intr: PIO transfer [%d], %d->%d phase %d stat %x intr %x\n",
|
|
*fsc->sc_pdmalen, fsc->sc_dmasize, cnt, flscphase, flscstat, flscintr));
|
|
sc->sc_phase = flscphase;
|
|
sc->sc_espstat = (u_char) flscstat;
|
|
sc->sc_espintr = (u_char) flscintr;
|
|
*fsc->sc_dmaaddr = p;
|
|
*fsc->sc_pdmalen -= fsc->sc_dmasize - cnt;
|
|
fsc->sc_dmasize = cnt;
|
|
|
|
if (*fsc->sc_pdmalen == 0) {
|
|
sc->sc_espstat |= NCRSTAT_TC;
|
|
fsc->sc_piomode = 0;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
int
|
|
flsc_dma_setup(struct ncr53c9x_softc *sc, caddr_t *addr, size_t *len,
|
|
int datain, size_t *dmasize)
|
|
{
|
|
struct flsc_softc *fsc = (struct flsc_softc *)sc;
|
|
paddr_t pa;
|
|
u_char *ptr;
|
|
size_t xfer;
|
|
|
|
fsc->sc_dmaaddr = addr;
|
|
fsc->sc_pdmalen = len;
|
|
fsc->sc_datain = datain;
|
|
fsc->sc_dmasize = *dmasize;
|
|
if (sc->sc_nexus->xs->xs_control & XS_CTL_POLL) {
|
|
/* polling mode, use PIO */
|
|
*dmasize = fsc->sc_dmasize;
|
|
NCR_DMA(("pfsc_dma_setup: PIO %p/%d [%d]\n", *addr,
|
|
fsc->sc_dmasize, *len));
|
|
fsc->sc_piomode = 1;
|
|
if (datain == 0) {
|
|
int n;
|
|
n = fsc->sc_dmasize;
|
|
if (n > 16)
|
|
n = 16;
|
|
while (n-- > 0) {
|
|
fsc->sc_reg[NCR_FIFO * 4] = **fsc->sc_dmaaddr;
|
|
(*fsc->sc_pdmalen)--;
|
|
(*fsc->sc_dmaaddr)++;
|
|
--fsc->sc_dmasize;
|
|
}
|
|
}
|
|
return 0;
|
|
}
|
|
/*
|
|
* DMA can be nasty for high-speed serial input, so limit the
|
|
* size of this DMA operation if the serial port is running at
|
|
* a high speed (higher than 19200 for now - should be adjusted
|
|
* based on CPU type and speed?).
|
|
* XXX - add serial speed check XXX
|
|
*/
|
|
if (ser_open_speed > 19200 && flsc_max_dma != 0 &&
|
|
fsc->sc_dmasize > flsc_max_dma)
|
|
fsc->sc_dmasize = flsc_max_dma;
|
|
ptr = *addr; /* Kernel virtual address */
|
|
pa = kvtop(ptr); /* Physical address of DMA */
|
|
xfer = min(fsc->sc_dmasize, PAGE_SIZE - (pa & (PAGE_SIZE - 1)));
|
|
fsc->sc_xfr_align = 0;
|
|
fsc->sc_piomode = 0;
|
|
fsc->sc_portbits &= ~FLSC_PB_DMA_BITS;
|
|
fsc->sc_reg[0x40] = fsc->sc_portbits;
|
|
fsc->sc_reg[0x80] = 0;
|
|
*((u_long *)fsc->sc_dmabase) = 0;
|
|
|
|
/*
|
|
* If output and length < 16, copy to fifo
|
|
*/
|
|
if (datain == 0 && fsc->sc_dmasize < 16) {
|
|
int n;
|
|
for (n = 0; n < fsc->sc_dmasize; ++n)
|
|
fsc->sc_reg[NCR_FIFO * 4] = *ptr++;
|
|
NCR_DMA(("flsc_dma_setup: %d bytes written to fifo\n", n));
|
|
fsc->sc_piomode = 1;
|
|
fsc->sc_active = 1;
|
|
*fsc->sc_pdmalen -= fsc->sc_dmasize;
|
|
*fsc->sc_dmaaddr += fsc->sc_dmasize;
|
|
*dmasize = fsc->sc_dmasize;
|
|
fsc->sc_dmasize = 0;
|
|
return 0; /* All done */
|
|
}
|
|
/*
|
|
* If output and unaligned, copy unaligned data to fifo
|
|
*/
|
|
else if (datain == 0 && (int)ptr & 3) {
|
|
int n = 4 - ((int)ptr & 3);
|
|
NCR_DMA(("flsc_dma_setup: align %d bytes written to fifo\n", n));
|
|
pa += n;
|
|
xfer -= n;
|
|
while (n--)
|
|
fsc->sc_reg[NCR_FIFO * 4] = *ptr++;
|
|
}
|
|
/*
|
|
* If unaligned address, read unaligned bytes into alignment buffer
|
|
*/
|
|
else if ((int)ptr & 3 || xfer & 3) {
|
|
pa = kvtop((caddr_t)fsc->sc_alignbuf);
|
|
xfer = fsc->sc_dmasize = min(xfer, sizeof (fsc->sc_unalignbuf));
|
|
NCR_DMA(("flsc_dma_setup: align read by %d bytes\n", xfer));
|
|
fsc->sc_xfr_align = 1;
|
|
}
|
|
/*
|
|
* If length smaller than longword, read into alignment buffer
|
|
* XXX doesn't work for 1 or 2 bytes !!!!
|
|
*/
|
|
else if (fsc->sc_dmasize < 4) {
|
|
NCR_DMA(("flsc_dma_setup: read remaining %d bytes\n",
|
|
fsc->sc_dmasize));
|
|
pa = kvtop((caddr_t)fsc->sc_alignbuf);
|
|
fsc->sc_xfr_align = 1;
|
|
}
|
|
/*
|
|
* Finally, limit transfer length to multiple of 4 bytes.
|
|
*/
|
|
else {
|
|
fsc->sc_dmasize &= -4;
|
|
xfer &= -4;
|
|
}
|
|
|
|
while (xfer < fsc->sc_dmasize) {
|
|
if ((pa + xfer) != kvtop(*addr + xfer))
|
|
break;
|
|
if ((fsc->sc_dmasize - xfer) < PAGE_SIZE)
|
|
xfer = fsc->sc_dmasize;
|
|
else
|
|
xfer += PAGE_SIZE;
|
|
}
|
|
|
|
fsc->sc_dmasize = xfer;
|
|
*dmasize = fsc->sc_dmasize;
|
|
fsc->sc_pa = pa;
|
|
#if defined(M68040) || defined(M68060)
|
|
if (mmutype == MMU_68040) {
|
|
if (fsc->sc_xfr_align) {
|
|
int n;
|
|
for (n = 0; n < sizeof (fsc->sc_unalignbuf); ++n)
|
|
fsc->sc_alignbuf[n] = n | 0x80;
|
|
dma_cachectl(fsc->sc_alignbuf,
|
|
sizeof(fsc->sc_unalignbuf));
|
|
}
|
|
else
|
|
dma_cachectl(*fsc->sc_dmaaddr, fsc->sc_dmasize);
|
|
}
|
|
#endif
|
|
fsc->sc_reg[0x80] = 0;
|
|
*((u_long *)(fsc->sc_dmabase + (pa & 0x00fffffc))) = pa;
|
|
fsc->sc_portbits &= ~FLSC_PB_DMA_BITS;
|
|
fsc->sc_portbits |= FLSC_PB_ENABLE_DMA |
|
|
(fsc->sc_datain ? FLSC_PB_DMA_READ : FLSC_PB_DMA_WRITE);
|
|
fsc->sc_reg[0x40] = fsc->sc_portbits;
|
|
NCR_DMA(("flsc_dma_setup: DMA %p->%lx/%d [%d]\n",
|
|
ptr, pa, fsc->sc_dmasize, *len));
|
|
fsc->sc_active = 1;
|
|
return 0;
|
|
}
|
|
|
|
void
|
|
flsc_dma_go(struct ncr53c9x_softc *sc)
|
|
{
|
|
struct flsc_softc *fsc = (struct flsc_softc *)sc;
|
|
|
|
NCR_DMA(("flsc_dma_go: datain %d size %d\n", fsc->sc_datain,
|
|
fsc->sc_dmasize));
|
|
if (sc->sc_nexus->xs->xs_control & XS_CTL_POLL) {
|
|
fsc->sc_active = 1;
|
|
return;
|
|
} else if (fsc->sc_piomode == 0) {
|
|
fsc->sc_portbits &= ~FLSC_PB_DMA_BITS;
|
|
fsc->sc_portbits |= FLSC_PB_ENABLE_DMA |
|
|
(fsc->sc_datain ? FLSC_PB_DMA_READ : FLSC_PB_DMA_WRITE);
|
|
fsc->sc_reg[0x40] = fsc->sc_portbits;
|
|
}
|
|
}
|
|
|
|
void
|
|
flsc_dma_stop(struct ncr53c9x_softc *sc)
|
|
{
|
|
struct flsc_softc *fsc = (struct flsc_softc *)sc;
|
|
|
|
fsc->sc_portbits &= ~FLSC_PB_DMA_BITS;
|
|
fsc->sc_reg[0x40] = fsc->sc_portbits;
|
|
|
|
fsc->sc_reg[0x80] = 0;
|
|
*((u_long *)fsc->sc_dmabase) = 0;
|
|
fsc->sc_piomode = 0;
|
|
}
|
|
|
|
int
|
|
flsc_dma_isactive(struct ncr53c9x_softc *sc)
|
|
{
|
|
struct flsc_softc *fsc = (struct flsc_softc *)sc;
|
|
|
|
return fsc->sc_active;
|
|
}
|