189 lines
7.1 KiB
C
189 lines
7.1 KiB
C
/* $NetBSD: omap3_sdmareg.h,v 1.4 2014/07/30 12:45:44 macallan Exp $ */
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/*
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* Copyright (c) 2012 Michael Lorenz
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: omap3_sdmareg.h,v 1.4 2014/07/30 12:45:44 macallan Exp $");
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#ifndef OMAPDMA_REG_H
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#define OMAPDMA_REG_H
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/*
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* all register offsets are relative to OMAP3530_SDMA_BASE
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*/
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#define OMAPDMA_REVISION 0x00000000
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/* each bit corresponds to a DMA channel, write 1 to clear */
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#define OMAPDMA_IRQSTATUS_L0 0x00000008
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#define OMAPDMA_IRQSTATUS_L1 0x0000000c
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#define OMAPDMA_IRQSTATUS_L2 0x00000010
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#define OMAPDMA_IRQSTATUS_L3 0x00000014
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#define OMAPDMA_IRQENABLE_L0 0x00000018
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#define OMAPDMA_IRQENABLE_L1 0x0000001c
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#define OMAPDMA_IRQENABLE_L2 0x00000020
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#define OMAPDMA_IRQENABLE_L3 0x00000024
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#define OMAPDMA_SYSSTATUS 0x00000028
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#define OMAPDMA_RESET_DONE 0x00000001
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#define OMAPDMA_SYSCONFIG 0x0000002c
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#define OMAPDMA_IDLEMODE_MASK 0x00003000
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#define OMAPDMA_IDLEMODE_FORCE_STANDBY 0x00000000
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#define OMAPDMA_IDLEMODE_NO_STANDBY 0x00001000
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#define OMAPDMA_IDLEMODE_SMART_STANDBY 0x00002000
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#define OMAPDMA_CLKACT_MASK 0x00000300
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#define OMAPDMA_EMUFREE 0x00000020
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#define OMAPDMA_SIDLEMODE_MASK 0x00000018
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#define OMAPDMA_FORCE_IDLE 0x00000000
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#define OMAPDMA_NO_IDLE 0x00000008
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#define OMAPDMA_SMART_IDLE 0x00000010
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#define OMAPDMA_SOFTRESET 0x00000002
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#define OMAPDMA_AUTOIDLE 0x00000001
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/* capability registers */
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#define OMAPDMA_CAPS_0 0x00000064
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#define OMAPDMA_CAP_FILL 0x00080000 /* fill support */
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#define OMAPDMA_CAP_TRANS_BLT 0x00040000 /* transparent blit */
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#define OMAPDMA_CAPS_2 0x0000006c
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#define OMAPDMA_CAPS_3 0x00000070
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#define OMAPDMA_CAPS_4 0x00000074
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#define OMAPDMA_GCR 0x00000078
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#define OMAPDMA_GCR_ARB_RATE_MASK 0x00ff0000
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#define OMAPDMA_GCR_ARB_RATE_SHIFT 16
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#define OMAPDMA_GCR_FIFO_BUDGET_NONE 0x00000000
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#define OMAPDMA_GCR_FIFO_BUDGET_75L 0x00004000
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#define OMAPDMA_GCR_FIFO_BUDGET_25L 0x00008000
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#define OMAPDMA_GCR_FIFO_BUDGET_50L 0x0000c000
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#define OMAPDMA_GCR_HI_THREAD_NONE 0x00000000
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#define OMAPDMA_GCR_HI_THREAD_0 0x00001000
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#define OMAPDMA_GCR_HI_THREAD_01 0x00002000
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#define OMAPDMA_GCR_HI_THREAD_012 0x00003000
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#define OMAPDMA_GCR_MAX_FIFO_DEPTH_MASK 0x000000ff
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/*
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* there are 32 channels, each occupies a 0x60 register space starting at
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* 0x00000080 + 0x60 * c for c = 0 .. 31
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*/
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#define OMAPDMA_CHANNEL_BASE 0x00000080
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#define OMAPDMAC_CCR 0x00000000
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#define CCR_WRITE_PRIORITY 0x04000000
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#define CCR_BUFFERING_DISABLE 0x02000000
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#define CCR_SEL_SRC_DST_SYNC 0x01000000
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#define CCR_PREFETCH 0x00800000
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#define CCR_SUPERVISOR 0x00400000
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#define CCR_SYNC_CONTROL_UPPER_MASK 0x00180000
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#define CCR_BLOCK_SYNC 0x00040000
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#define CCR_TRANSPARENT_COPY_ENABLE 0x00020000
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#define CCR_CONST_FILL_ENABLE 0x00010000
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#define CCR_DST_AMODE_MASK 0x0000c000
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#define CCR_DST_AMODE_CONST_ADDR 0x00000000
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#define CCR_DST_AMODE_POST_INCR 0x00004000
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#define CCR_DST_AMODE_SINGLE_INDEX 0x00008000
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#define CCR_DST_AMODE_DOUBLE_INDEX 0x0000c000
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#define CCR_SRC_AMODE_MASK 0x00003000
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#define CCR_SRC_AMODE_CONST_ADDR 0x00000000
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#define CCR_SRC_AMODE_POST_INCR 0x00001000
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#define CCR_SRC_AMODE_SINGLE_INDEX 0x00002000
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#define CCR_SRC_AMODE_DOUBLE_INDEX 0x00003000
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#define CCR_WR_ACTIVE 0x00000400
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#define CCR_RD_ACTIVE 0x00000200
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#define CCR_SUSPEND_SENSITIVE 0x00000100
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#define CCR_ENABLE 0x00000080
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#define CCR_READ_PRIORITY 0x00000040
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#define CCR_FRAME_SYNC 0x00000020
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#define CCR_SYNCHRO_CONTROL_MASK 0x0000001f
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#define OMAPDMAC_CLNK_CTRL 0x00000004
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#define CLNK_ENABLE_LNK 0x00008000
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#define CLNK_NEXT_CHANNEL_MASK 0x0000001f
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#define OMAPDMAC_CICRI 0x00000008
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#define CICRI_DRAIN_IE 0x00001000
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#define CICRI_MISALIGNED_ERR_IE 0x00000800
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#define CICRI_SUPERVISOR_ERR_IE 0x00000400
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#define CICRI_TRANSFER_ERR_IE 0x00000100
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#define CICRI_PKT_IE 0x00000080
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#define CICRI_BLOCK_IE 0x00000020
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#define CICRI_LAST_IE 0x00000010
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#define CICRI_FRAME_IE 0x00000008
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#define CICRI_HALF_IE 0x00000004
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#define CICRI_DROP_IE 0x00000002
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#define OMAPDMAC_CSR 0x0000000c
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#define CSR_DRAIN_END 0x00001000
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#define CSR_MISALIGNED_ADRS_ERR 0x00000800
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#define CSR_SUPERVISOR_ERR 0x00000400
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#define CSR_TRANS_ERR 0x00000100
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#define CSR_PKT 0x00000080
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#define CSR_SYNC 0x00000040
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#define CSR_BLOCK 0x00000020
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#define CSR_LAST 0x00000010
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#define CSR_FRAME 0x00000008
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#define CSR_HALF 0x00000004
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#define CSR_DROP 0x00000002
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#define OMAPDMAC_CSDPI 0x00000010
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#define CSDPI_SRC_ENDIAN 0x00100000
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#define CSDPI_SRC_ENDIAN_LOCK 0x00080000
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#define CSDPI_DST_ENDIAN 0x00040000
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#define CSDPI_DST_ENDIAN_LOCK 0x00020000
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#define CSDPI_WRITE_MODE_MASK 0x00018000
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#define CSDPI_WRITE_NONPOSTED 0x00000000
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#define CSDPI_WRITE_POSTED 0x00008000
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#define CSDPI_WRITE_POSTED_EXCEPT_LAST 0x00010000
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#define CSDPI_DST_BURST_MASK 0x0000c000
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#define CSDPI_DST_BURST_SINGLE 0x00000000
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#define CSDPI_DST_BURST_16 0x00004000
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#define CSDPI_DST_BURST_32 0x00008000
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#define CSDPI_DST_BURST_64 0x0000c000
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#define CSDPI_DST_PACKED 0x00002000
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#define CSDPI_SRC_BURST_MASK 0x00000180
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#define CSDPI_SRC_BURST_SINGLE 0x00000000
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#define CSDPI_SRC_BURST_16 0x00000080
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#define CSDPI_SRC_BURST_32 0x00000100
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#define CSDPI_SRC_BURST_64 0x00000180
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#define CSDPI_SRC_PACKED 0x00000040
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#define CSDPI_DATA_TYPE_MASK 0x00000003
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#define CSDPI_DATA_TYPE_8 0x00000000
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#define CSDPI_DATA_TYPE_16 0x00000001
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#define CSDPI_DATA_TYPE_32 0x00000002
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#define OMAPDMAC_CEN 0x00000014
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#define OMAPDMAC_CFN 0x00000018
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#define OMAPDMAC_CSSA 0x0000001c
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#define OMAPDMAC_CDSA 0x00000020
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#define OMAPDMAC_CSEI 0x00000024
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#define OMAPDMAC_CSFI 0x00000028
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#define OMAPDMAC_CDEI 0x0000002c
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#define OMAPDMAC_CDFI 0x00000030
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#define OMAPDMAC_CSAC 0x00000034
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#define OMAPDMAC_CDAC 0x00000038
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#define OMAPDMAC_CCEN 0x0000003c
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#define OMAPDMAC_CCFN 0x00000040
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#define OMAPDMAC_COLOR 0x00000044
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#endif /* OMAPDMA_REG_H */
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