249 lines
9.5 KiB
C
249 lines
9.5 KiB
C
/* $NetBSD: specialreg.h,v 1.11 2000/03/27 23:15:57 thorpej Exp $ */
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/*-
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* Copyright (c) 1991 The Regents of the University of California.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the University of
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* California, Berkeley and its contributors.
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* 4. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* @(#)specialreg.h 7.1 (Berkeley) 5/9/91
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*/
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/*
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* Bits in 386 special registers:
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*/
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#define CR0_PE 0x00000001 /* Protected mode Enable */
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#define CR0_MP 0x00000002 /* "Math" Present (NPX or NPX emulator) */
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#define CR0_EM 0x00000004 /* EMulate non-NPX coproc. (trap ESC only) */
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#define CR0_TS 0x00000008 /* Task Switched (if MP, trap ESC and WAIT) */
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#define CR0_ET 0x00000010 /* Extension Type (387 (if set) vs 287) */
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#define CR0_PG 0x80000000 /* PaGing enable */
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/*
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* Bits in 486 special registers:
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*/
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#define CR0_NE 0x00000020 /* Numeric Error enable (EX16 vs IRQ13) */
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#define CR0_WP 0x00010000 /* Write Protect (honor PG_RW in all modes) */
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#define CR0_AM 0x00040000 /* Alignment Mask (set to enable AC flag) */
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#define CR0_NW 0x20000000 /* Not Write-through */
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#define CR0_CD 0x40000000 /* Cache Disable */
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/*
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* Cyrix 486 DLC special registers, accessable as IO ports.
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*/
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#define CCR0 0xc0 /* configuration control register 0 */
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#define CCR0_NC0 0x01 /* first 64K of each 1M memory region is non-cacheable */
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#define CCR0_NC1 0x02 /* 640K-1M region is non-cacheable */
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#define CCR0_A20M 0x04 /* enables A20M# input pin */
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#define CCR0_KEN 0x08 /* enables KEN# input pin */
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#define CCR0_FLUSH 0x10 /* enables FLUSH# input pin */
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#define CCR0_BARB 0x20 /* flushes internal cache when entering hold state */
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#define CCR0_CO 0x40 /* cache org: 1=direct mapped, 0=2x set assoc */
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#define CCR0_SUSPEND 0x80 /* enables SUSP# and SUSPA# pins */
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#define CCR1 0xc1 /* configuration control register 1 */
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#define CCR1_RPL 0x01 /* enables RPLSET and RPLVAL# pins */
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/* the remaining 7 bits of this register are reserved */
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/*
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* bits in the pentiums %cr4 register:
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*/
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#define CR4_VME 0x00000001 /* virtual 8086 mode extension enable */
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#define CR4_PVI 0x00000002 /* protected mode virtual interrupt enable */
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#define CR4_TSD 0x00000004 /* restrict RDTSC instruction to cpl 0 only */
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#define CR4_DE 0x00000008 /* debugging extension */
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#define CR4_PSE 0x00000010 /* large (4MB) page size enable */
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#define CR4_PAE 0x00000020 /* physical address extension enable */
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#define CR4_MCE 0x00000040 /* machine check enable */
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#define CR4_PGE 0x00000080 /* page global enable */
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#define CR4_PCE 0x00000100 /* enable RDPMC instruction for all cpls */
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/*
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* CPUID "features" bits:
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*/
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#define CPUID_FPU 0x00000001 /* processor has an FPU? */
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#define CPUID_VME 0x00000002 /* has virtual mode (%cr4's VME/PVI) */
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#define CPUID_DE 0x00000004 /* has debugging extension */
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#define CPUID_PSE 0x00000008 /* has page 4MB page size extension */
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#define CPUID_TSC 0x00000010 /* has time stamp counter */
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#define CPUID_MSR 0x00000020 /* has mode specific registers */
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#define CPUID_PAE 0x00000040 /* has phys address extension */
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#define CPUID_MCE 0x00000080 /* has machine check exception */
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#define CPUID_CX8 0x00000100 /* has CMPXCHG8B instruction */
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#define CPUID_APIC 0x00000200 /* has enabled APIC */
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#define CPUID_B10 0x00000400 /* reserved, MTRR */
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#define CPUID_SEP 0x00000800 /* has SYSENTER/SYSEXIT extension */
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#define CPUID_MTRR 0x00001000 /* has memory type range register */
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#define CPUID_PGE 0x00002000 /* has page global extension */
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#define CPUID_MCA 0x00004000 /* has machine check architecture */
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#define CPUID_CMOV 0x00008000 /* has CMOVcc instruction */
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#define CPUID_FGPAT 0x00010000 /* Page Attribute Table */
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#define CPUID_PSE36 0x00020000 /* 36-bit PSE */
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#define CPUID_PN 0x00040000 /* processor serial number */
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#define CPUID_B19 0x00080000 /* reserved */
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#define CPUID_B20 0x00100000 /* reserved */
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#define CPUID_B21 0x00200000 /* reserved */
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#define CPUID_B22 0x00400000 /* reserved */
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#define CPUID_MMX 0x00800000 /* MMX supported */
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#define CPUID_FXSR 0x01000000 /* fast FP/MMX save/restore */
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#define CPUID_XMM 0x02000000 /* streaming SIMD extensions */
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/* bits 26->31 also reserved. */
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#define CPUID_FLAGS1 "\20\1FPU\2VME\3DE\4PSE\5TSC\6MSR\7PAE\10MCE\11CX8\12APIC\13B10\14SEP\15MTRR"
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#define CPUID_FLAGS2 "\20\16PGE\17MCA\20CMOV\21FGPAT\22PSE36\23PN\24B19\25B20\26B21\27B22\30MMX\31FXSR\32XMM\33B26\34B27\35B28\36B29\37B30\40B31"
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/*
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* Model-specific registers for the i386 family
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*/
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#define MSR_P5_MC_ADDR 0x000 /* P5 only */
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#define MSR_P5_MC_TYPE 0x001 /* P5 only */
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#define MSR_TSC 0x010
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#define MSR_CESR 0x011 /* P5 only (trap on P6) */
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#define MSR_CTR0 0x012 /* P5 only (trap on P6) */
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#define MSR_CTR1 0x013 /* P5 only (trap on P6) */
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#define MSR_APICBASE 0x01b
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#define MSR_EBL_CR_POWERON 0x02a
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#define MSR_TEST_CTL 0x033
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#define MSR_BIOS_UPDT_TRIG 0x079
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#define MSR_BBL_CR_D0 0x088 /* PII+ only */
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#define MSR_BBL_CR_D1 0x089 /* PII+ only */
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#define MSR_BBL_CR_D2 0x08a /* PII+ only */
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#define MSR_BIOS_SIGN 0x08b
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#define MSR_PERFCTR0 0x0c1
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#define MSR_PERFCTR1 0x0c2
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#define MSR_MTRRcap 0x0fe
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#define MSR_BBL_CR_ADDR 0x116 /* PII+ only */
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#define MSR_BBL_CR_DECC 0x118 /* PII+ only */
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#define MSR_BBL_CR_CTL 0x119 /* PII+ only */
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#define MSR_BBL_CR_TRIG 0x11a /* PII+ only */
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#define MSR_BBL_CR_BUSY 0x11b /* PII+ only */
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#define MSR_BBL_CR_CTR3 0x11e /* PII+ only */
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#define MSR_MCG_CAP 0x179
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#define MSR_MCG_STATUS 0x17a
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#define MSR_MCG_CTL 0x17b
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#define MSR_EVNTSEL0 0x186
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#define MSR_EVNTSEL1 0x187
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#define MSR_DEBUGCTLMSR 0x1d9
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#define MSR_LASTBRANCHFROMIP 0x1db
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#define MSR_LASTBRANCHTOIP 0x1dc
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#define MSR_LASTINTFROMIP 0x1dd
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#define MSR_LASTINTTOIP 0x1de
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#define MSR_ROB_CR_BKUPTMPDR6 0x1e0
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#define MSR_MTRRphysBase0 0x200
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#define MSR_MTRRphysMask0 0x201
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#define MSR_MTRRphysBase1 0x202
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#define MSR_MTRRphysMask1 0x203
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#define MSR_MTRRphysBase2 0x204
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#define MSR_MTRRphysMask2 0x205
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#define MSR_MTRRphysBase3 0x206
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#define MSR_MTRRphysMask3 0x207
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#define MSR_MTRRphysBase4 0x208
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#define MSR_MTRRphysMask4 0x209
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#define MSR_MTRRphysBase5 0x20a
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#define MSR_MTRRphysMask5 0x20b
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#define MSR_MTRRphysBase6 0x20c
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#define MSR_MTRRphysMask6 0x20d
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#define MSR_MTRRphysBase7 0x20e
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#define MSR_MTRRphysMask7 0x20f
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#define MSR_MTRRfix64K_00000 0x250
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#define MSR_MTRRfix16K_80000 0x258
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#define MSR_MTRRfix16K_A0000 0x259
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#define MSR_MTRRfix4K_C0000 0x268
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#define MSR_MTRRfix4K_C8000 0x269
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#define MSR_MTRRfix4K_D0000 0x26a
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#define MSR_MTRRfix4K_D8000 0x26b
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#define MSR_MTRRfix4K_E0000 0x26c
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#define MSR_MTRRfix4K_E8000 0x26d
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#define MSR_MTRRfix4K_F0000 0x26e
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#define MSR_MTRRfix4K_F8000 0x26f
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#define MSR_MTRRdefType 0x2ff
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#define MSR_MC0_CTL 0x400
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#define MSR_MC0_STATUS 0x401
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#define MSR_MC0_ADDR 0x402
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#define MSR_MC0_MISC 0x403
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#define MSR_MC1_CTL 0x404
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#define MSR_MC1_STATUS 0x405
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#define MSR_MC1_ADDR 0x406
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#define MSR_MC1_MISC 0x407
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#define MSR_MC2_CTL 0x408
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#define MSR_MC2_STATUS 0x409
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#define MSR_MC2_ADDR 0x40a
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#define MSR_MC2_MISC 0x40b
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#define MSR_MC4_CTL 0x40c
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#define MSR_MC4_STATUS 0x40d
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#define MSR_MC4_ADDR 0x40e
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#define MSR_MC4_MISC 0x40f
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#define MSR_MC3_CTL 0x410
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#define MSR_MC3_STATUS 0x411
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#define MSR_MC3_ADDR 0x412
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#define MSR_MC3_MISC 0x413
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/*
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* Constants related to MTRRs
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*/
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#define MTRR_N64K 8 /* numbers of fixed-size entries */
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#define MTRR_N16K 16
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#define MTRR_N4K 64
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/*
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* the following four 3-byte registers control the non-cacheable regions.
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* These registers must be written as three seperate bytes.
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*
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* NCRx+0: A31-A24 of starting address
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* NCRx+1: A23-A16 of starting address
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* NCRx+2: A15-A12 of starting address | NCR_SIZE_xx.
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*
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* The non-cacheable region's starting address must be aligned to the
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* size indicated by the NCR_SIZE_xx field.
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*/
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#define NCR1 0xc4
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#define NCR2 0xc7
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#define NCR3 0xca
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#define NCR4 0xcd
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#define NCR_SIZE_0K 0
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#define NCR_SIZE_4K 1
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#define NCR_SIZE_8K 2
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#define NCR_SIZE_16K 3
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#define NCR_SIZE_32K 4
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#define NCR_SIZE_64K 5
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#define NCR_SIZE_128K 6
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#define NCR_SIZE_256K 7
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#define NCR_SIZE_512K 8
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#define NCR_SIZE_1M 9
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#define NCR_SIZE_2M 10
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#define NCR_SIZE_4M 11
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#define NCR_SIZE_8M 12
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#define NCR_SIZE_16M 13
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#define NCR_SIZE_32M 14
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#define NCR_SIZE_4G 15
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