149 lines
6.6 KiB
C
149 lines
6.6 KiB
C
/* $NetBSD: a12creg.h,v 1.2 1998/03/02 06:56:16 ross Exp $ */
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/* [Notice revision 2.0]
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* Copyright (c) 1997 Avalon Computer Systems, Inc.
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* All rights reserved.
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*
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* Author: Ross Harvey
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright and
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* author notice, this list of conditions, and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of Avalon Computer Systems, Inc. nor the names of
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* its contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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* 4. This copyright will be assigned to The NetBSD Foundation on
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* 1/1/2000 unless these terms (including possibly the assignment
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* date) are updated in writing by Avalon prior to the latest specified
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* assignment date.
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*
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* THIS SOFTWARE IS PROVIDED BY AVALON COMPUTER SYSTEMS, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _ALPHA_PCI_A12CREG_H_
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#define _ALPHA_PCI_A12CREG_H_
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#define A12CREG() /* generate ctags(1) key */
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#define REGADDR(r) ((volatile long *)ALPHA_PHYS_TO_K0SEG(r))
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#define REGVAL(r) (*REGADDR(r))
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/*
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* -- A d d r e s s L i n e --
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*
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* 39 36 29 28 27-13 12 .11 10 9 8-6 5 4 3
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*
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* IMALR 1 1 a a a-a a . a a a a-a 0 0
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* IMALR_LB 1 1 a a a-a a . a a a a-a 0 1
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* OMALR 1 1 a a a-a a . a a a a-a 1 0
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* OMALR_LB 1 1 a a a-a a . a a a a-a 1 1
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* MCRP 1 0 0 0 . 0 0 0 a-a a a a
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* MCRP_LWE 1 0 0 0 . 0 0 1 0 1
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* MCRP_LWO 1 0 0 0 . 0 1 0 1 1
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* MCSR 1 0 0 1 . 0 0 1 1
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* OMR 1 0 0 1 . 0 1 0 1
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* GSR 1 0 0 1 . 0 1 1 1
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* IETCR 1 0 0 1 . 1 0 0 1
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* CDR 1 0 0 1 . 1 0 1 1
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* PMEM 1 0 0 1 . 1 1 0 1
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* SOR 1 0 0 1 . 1 1 1 1
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* PCI Buffer 1 0 1 0 a-a a . a a a a a a
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* PCI Target 1 0 1 1 a-a a . a a a a a a
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* Main Memory 0 0 a a a-a a . a a a a a a
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*
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*
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*/
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#define _A12_IO 0x8000000000L
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#define A12_OFFS_FIFO 0x0000
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#define A12_OFFS_FIFO_LWE 0x0200
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#define A12_OFFS_FIFO_LWO 0x0400
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#define A12_OFFS_VERS 0x1010
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#define A12_OFFS_MCSR 0x1210
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#define A12_OFFS_OMR 0x1410
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#define A12_OFFS_GSR 0x1610
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#define A12_OFFS_IETCR 0x1810
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#define A12_OFFS_CDR 0x1a10
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#define A12_OFFS_PMEM 0x1c10
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#define A12_OFFS_SOR 0x1e10
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#define A12_FIFO (_A12_IO|A12_OFFS_FIFO)
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#define A12_FIFO_LWE (_A12_IO|A12_OFFS_FIFO_LWE)
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#define A12_FIFO_LWO (_A12_IO|A12_OFFS_FIFO_LWO)
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#define A12_VERS (_A12_IO|A12_OFFS_VERS)
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#define A12_MCSR (_A12_IO|A12_OFFS_MCSR)
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#define A12_OMR (_A12_IO|A12_OFFS_OMR)
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#define A12_GSR (_A12_IO|A12_OFFS_GSR)
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#define A12_IETCR (_A12_IO|A12_OFFS_IETCR)
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#define A12_CDR (_A12_IO|A12_OFFS_CDR)
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#define A12_PMEM (_A12_IO|A12_OFFS_PMEM)
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#define A12_SOR (_A12_IO|A12_OFFS_SOR)
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#define A12_PCIBuffer 0x8020000000L
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#define A12_PCITarget 0x8030000000L
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#define A12_PCIMasterAbort 0x8000 /* GSR */
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#define A12_OMR_PCIAddr2 0x1000L /* OMR */
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#define A12_OMR_PCIConfigCycle 0x0800L /* OMR */
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#define A12_OMR_ICW_ENABLE 0x0400L /* OMR */
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#define A12_OMR_IEI_ENABLE 0x0200L /* OMR */
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#define A12_OMR_TEI_ENABLE 0x0100L /* OMR */
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#define A12_OMR_PCI_ENABLE 0x0080L /* OMR */
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#define A12_OMR_OMF_ENABLE 0x0040L /* OMR */
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#define A12_MCSR_DMAOUT 0x4000 /* Outgoing DMA channel armed */
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#define A12_MCSR_DMAIN 0x2000 /* Incoming DMA channel armed */
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#define A12_MCSR_OMFE 0x1000 /* Outgoing message fifo empty */
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#define A12_MCSR_OMFF 0x0800 /* Outgoing message fifo full */
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#define A12_MCSR_OMFAF 0x0400 /* Outgoing message fifo almost full */
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#define A12_MCSR_IMFAE 0x0200 /* Incoming message fifo almost empty */
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#define A12_MCSR_IMP 0x0100 /* Incoming message pending */
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#define A12_MCSR_TBC 0x0080 /* Transmit Block Complete */
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#define A12_MCSR_RBC 0x0040 /* Receive Block Complete */
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#define A12_GSR_PDI 0x0040 /* PCI device interrupt asserted */
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#define A12_GSR_PEI 0x0080 /* PCI SERR# pulse received */
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#define A12_GSR_MCE 0x0100 /* Missing Close Error Flag */
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#define A12_GSR_ECE 0x0200 /* Embedded Close Error Flag */
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#define A12_GSR_TEI 0x0400 /* Timer event interrupt pending */
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#define A12_GSR_IEI 0x0800 /* Interval event interrupt pending */
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#define A12_GSR_FORUN 0x1000 /* FIFO Overrun Error */
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#define A12_GSR_FURUN 0x2000 /* FIFO Underrun Error */
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#define A12_GSR_ICW 0x4000 /* Incoming Control Word */
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#define A12_GSR_ABORT 0x8000 /* PCI Master or Target Abort */
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#define A12_ALL_WIRED 0xffc0 /* Core logic wires these bits */
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#define A12_ALL_FIRST 6 /* ...starting at this one */
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#define A12_ALL_EXTRACT(r) (((r) & A12_ALL_WIRED) >> A12_ALL_FIRST)
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#define A12_CBMAOFFSET 0x0100
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#define A12_XBAR_CHANNEL_MAX 14
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#define A12_TMP_PID_COUNT 12
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#define A12CONS_CPU_LOCAL 0x40 /* our switch channel */
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#define A12CONS_CPU_ETHER 0x41 /* route to outside world */
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#define A12CONS_CPU_GLOBAL 0x42 /* location in the big picture */
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#define DIE() NICETRY()
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#define NICETRY() panic("Nice try @ %s:%d\n", __FILE__, __LINE__)
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#define What() printf("%s:%d. What?\n", __FILE__, __LINE__)
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#endif
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