525 lines
17 KiB
C
525 lines
17 KiB
C
/* $NetBSD: siside.c,v 1.13 2004/08/21 00:28:34 thorpej Exp $ */
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/*
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* Copyright (c) 1999, 2000, 2001 Manuel Bouyer.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Manuel Bouyer.
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* 4. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <dev/pci/pcivar.h>
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#include <dev/pci/pcidevs.h>
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#include <dev/pci/pciidereg.h>
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#include <dev/pci/pciidevar.h>
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#include <dev/pci/pciide_sis_reg.h>
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static void sis_chip_map(struct pciide_softc *, struct pci_attach_args *);
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static void sis_sata_chip_map(struct pciide_softc *, struct pci_attach_args *);
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static void sis_setup_channel(struct ata_channel *);
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static void sis96x_setup_channel(struct ata_channel *);
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static int sis_hostbr_match(struct pci_attach_args *);
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static int sis_south_match(struct pci_attach_args *);
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static int siside_match(struct device *, struct cfdata *, void *);
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static void siside_attach(struct device *, struct device *, void *);
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CFATTACH_DECL(siside, sizeof(struct pciide_softc),
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siside_match, siside_attach, NULL, NULL);
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static const struct pciide_product_desc pciide_sis_products[] = {
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{ PCI_PRODUCT_SIS_5597_IDE,
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0,
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NULL,
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sis_chip_map,
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},
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{ PCI_PRODUCT_SIS_180_SATA,
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0,
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NULL,
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sis_sata_chip_map,
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},
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{ 0,
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0,
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NULL,
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NULL
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}
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};
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static int
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siside_match(struct device *parent, struct cfdata *match, void *aux)
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{
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struct pci_attach_args *pa = aux;
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if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_SIS) {
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if (pciide_lookup_product(pa->pa_id, pciide_sis_products))
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return (2);
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}
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return (0);
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}
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static void
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siside_attach(struct device *parent, struct device *self, void *aux)
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{
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struct pci_attach_args *pa = aux;
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struct pciide_softc *sc = (struct pciide_softc *)self;
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pciide_common_attach(sc, pa,
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pciide_lookup_product(pa->pa_id, pciide_sis_products));
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}
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static struct sis_hostbr_type {
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u_int16_t id;
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u_int8_t rev;
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u_int8_t udma_mode;
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char *name;
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u_int8_t type;
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#define SIS_TYPE_NOUDMA 0
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#define SIS_TYPE_66 1
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#define SIS_TYPE_100OLD 2
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#define SIS_TYPE_100NEW 3
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#define SIS_TYPE_133OLD 4
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#define SIS_TYPE_133NEW 5
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#define SIS_TYPE_SOUTH 6
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} sis_hostbr_type[] = {
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/* Most infos here are from sos@freebsd.org */
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{PCI_PRODUCT_SIS_530HB, 0x00, 4, "530", SIS_TYPE_66},
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#if 0
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/*
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* controllers associated to a rev 0x2 530 Host to PCI Bridge
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* have problems with UDMA (info provided by Christos)
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*/
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{PCI_PRODUCT_SIS_530HB, 0x02, 0, "530 (buggy)", SIS_TYPE_NOUDMA},
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#endif
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{PCI_PRODUCT_SIS_540HB, 0x00, 4, "540", SIS_TYPE_66},
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{PCI_PRODUCT_SIS_550HB, 0x00, 4, "550", SIS_TYPE_66},
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{PCI_PRODUCT_SIS_620, 0x00, 4, "620", SIS_TYPE_66},
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{PCI_PRODUCT_SIS_630, 0x00, 4, "630", SIS_TYPE_66},
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{PCI_PRODUCT_SIS_630, 0x30, 5, "630S", SIS_TYPE_100NEW},
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{PCI_PRODUCT_SIS_633, 0x00, 5, "633", SIS_TYPE_100NEW},
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{PCI_PRODUCT_SIS_635, 0x00, 5, "635", SIS_TYPE_100NEW},
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{PCI_PRODUCT_SIS_640, 0x00, 4, "640", SIS_TYPE_SOUTH},
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{PCI_PRODUCT_SIS_645, 0x00, 6, "645", SIS_TYPE_SOUTH},
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{PCI_PRODUCT_SIS_646, 0x00, 6, "645DX", SIS_TYPE_SOUTH},
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{PCI_PRODUCT_SIS_648, 0x00, 6, "648", SIS_TYPE_SOUTH},
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{PCI_PRODUCT_SIS_650, 0x00, 6, "650", SIS_TYPE_SOUTH},
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{PCI_PRODUCT_SIS_651, 0x00, 6, "651", SIS_TYPE_SOUTH},
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{PCI_PRODUCT_SIS_652, 0x00, 6, "652", SIS_TYPE_SOUTH},
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{PCI_PRODUCT_SIS_655, 0x00, 6, "655", SIS_TYPE_SOUTH},
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{PCI_PRODUCT_SIS_658, 0x00, 6, "658", SIS_TYPE_SOUTH},
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{PCI_PRODUCT_SIS_730, 0x00, 5, "730", SIS_TYPE_100OLD},
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{PCI_PRODUCT_SIS_733, 0x00, 5, "733", SIS_TYPE_100NEW},
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{PCI_PRODUCT_SIS_735, 0x00, 5, "735", SIS_TYPE_100NEW},
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{PCI_PRODUCT_SIS_740, 0x00, 5, "740", SIS_TYPE_SOUTH},
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{PCI_PRODUCT_SIS_741, 0x00, 5, "741", SIS_TYPE_SOUTH},
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{PCI_PRODUCT_SIS_745, 0x00, 5, "745", SIS_TYPE_100NEW},
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{PCI_PRODUCT_SIS_746, 0x00, 6, "746", SIS_TYPE_SOUTH},
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{PCI_PRODUCT_SIS_748, 0x00, 6, "748", SIS_TYPE_SOUTH},
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{PCI_PRODUCT_SIS_750, 0x00, 6, "750", SIS_TYPE_SOUTH},
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{PCI_PRODUCT_SIS_751, 0x00, 6, "751", SIS_TYPE_SOUTH},
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{PCI_PRODUCT_SIS_752, 0x00, 6, "752", SIS_TYPE_SOUTH},
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{PCI_PRODUCT_SIS_755, 0x00, 6, "755", SIS_TYPE_SOUTH},
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/*
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* From sos@freebsd.org: the 0x961 ID will never be found in real world
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* {PCI_PRODUCT_SIS_961, 0x00, 6, "961", SIS_TYPE_133NEW},
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*/
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{PCI_PRODUCT_SIS_962, 0x00, 6, "962", SIS_TYPE_133NEW},
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{PCI_PRODUCT_SIS_963, 0x00, 6, "963", SIS_TYPE_133NEW},
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{PCI_PRODUCT_SIS_964, 0x00, 6, "964", SIS_TYPE_133NEW},
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};
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static struct sis_hostbr_type *sis_hostbr_type_match;
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static int
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sis_hostbr_match(struct pci_attach_args *pa)
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{
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int i;
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if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_SIS)
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return 0;
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sis_hostbr_type_match = NULL;
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for (i = 0;
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i < sizeof(sis_hostbr_type) / sizeof(sis_hostbr_type[0]);
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i++) {
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if (PCI_PRODUCT(pa->pa_id) == sis_hostbr_type[i].id &&
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PCI_REVISION(pa->pa_class) >= sis_hostbr_type[i].rev)
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sis_hostbr_type_match = &sis_hostbr_type[i];
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}
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return (sis_hostbr_type_match != NULL);
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}
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static int
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sis_south_match(struct pci_attach_args *pa)
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{
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return (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_SIS &&
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PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_SIS_85C503 &&
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PCI_REVISION(pa->pa_class) >= 0x10);
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}
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static void
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sis_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa)
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{
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struct pciide_channel *cp;
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int channel;
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u_int8_t sis_ctr0 = pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_CTRL0);
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pcireg_t interface = PCI_INTERFACE(pa->pa_class);
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pcireg_t rev = PCI_REVISION(pa->pa_class);
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bus_size_t cmdsize, ctlsize;
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if (pciide_chipen(sc, pa) == 0)
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return;
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aprint_normal("%s: Silicon Integrated Systems ",
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sc->sc_wdcdev.sc_atac.atac_dev.dv_xname);
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pci_find_device(NULL, sis_hostbr_match);
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if (sis_hostbr_type_match) {
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if (sis_hostbr_type_match->type == SIS_TYPE_SOUTH) {
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pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_REG_57,
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pciide_pci_read(sc->sc_pc, sc->sc_tag,
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SIS_REG_57) & 0x7f);
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if (PCI_PRODUCT(pci_conf_read(sc->sc_pc, sc->sc_tag,
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PCI_ID_REG)) == SIS_PRODUCT_5518) {
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aprint_normal("96X UDMA%d",
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sis_hostbr_type_match->udma_mode);
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sc->sis_type = SIS_TYPE_133NEW;
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sc->sc_wdcdev.sc_atac.atac_udma_cap =
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sis_hostbr_type_match->udma_mode;
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} else {
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if (pci_find_device(NULL, sis_south_match)) {
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sc->sis_type = SIS_TYPE_133OLD;
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sc->sc_wdcdev.sc_atac.atac_udma_cap =
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sis_hostbr_type_match->udma_mode;
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} else {
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sc->sis_type = SIS_TYPE_100NEW;
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sc->sc_wdcdev.sc_atac.atac_udma_cap =
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sis_hostbr_type_match->udma_mode;
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}
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}
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} else {
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sc->sis_type = sis_hostbr_type_match->type;
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sc->sc_wdcdev.sc_atac.atac_udma_cap =
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sis_hostbr_type_match->udma_mode;
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}
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aprint_normal(sis_hostbr_type_match->name);
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} else {
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aprint_normal("5597/5598");
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if (rev >= 0xd0) {
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sc->sc_wdcdev.sc_atac.atac_udma_cap = 2;
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sc->sis_type = SIS_TYPE_66;
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} else {
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sc->sc_wdcdev.sc_atac.atac_udma_cap = 0;
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sc->sis_type = SIS_TYPE_NOUDMA;
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}
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}
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aprint_normal(" IDE controller (rev. 0x%02x)\n",
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PCI_REVISION(pa->pa_class));
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aprint_normal("%s: bus-master DMA support present",
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sc->sc_wdcdev.sc_atac.atac_dev.dv_xname);
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pciide_mapreg_dma(sc, pa);
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aprint_normal("\n");
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sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA16 | ATAC_CAP_DATA32;
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if (sc->sc_dma_ok) {
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sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA;
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sc->sc_wdcdev.irqack = pciide_irqack;
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if (sc->sis_type >= SIS_TYPE_66)
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sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA;
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}
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sc->sc_wdcdev.sc_atac.atac_pio_cap = 4;
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sc->sc_wdcdev.sc_atac.atac_dma_cap = 2;
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sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray;
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sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS;
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switch(sc->sis_type) {
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case SIS_TYPE_NOUDMA:
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case SIS_TYPE_66:
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case SIS_TYPE_100OLD:
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sc->sc_wdcdev.sc_atac.atac_set_modes = sis_setup_channel;
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pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_MISC,
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pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_MISC) |
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SIS_MISC_TIM_SEL | SIS_MISC_FIFO_SIZE | SIS_MISC_GTC);
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break;
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case SIS_TYPE_100NEW:
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case SIS_TYPE_133OLD:
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sc->sc_wdcdev.sc_atac.atac_set_modes = sis_setup_channel;
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pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_REG_49,
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pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_REG_49) | 0x01);
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break;
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case SIS_TYPE_133NEW:
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sc->sc_wdcdev.sc_atac.atac_set_modes = sis96x_setup_channel;
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pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_REG_50,
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pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_REG_50) & 0xf7);
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pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_REG_52,
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pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_REG_52) & 0xf7);
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break;
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}
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wdc_allocate_regs(&sc->sc_wdcdev);
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for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels;
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channel++) {
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cp = &sc->pciide_channels[channel];
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if (pciide_chansetup(sc, channel, interface) == 0)
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continue;
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if ((channel == 0 && (sis_ctr0 & SIS_CTRL0_CHAN0_EN) == 0) ||
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(channel == 1 && (sis_ctr0 & SIS_CTRL0_CHAN1_EN) == 0)) {
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aprint_normal("%s: %s channel ignored (disabled)\n",
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sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, cp->name);
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cp->ata_channel.ch_flags |= ATACH_DISABLED;
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continue;
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}
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pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize,
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pciide_pci_intr);
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}
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}
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static void
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sis96x_setup_channel(struct ata_channel *chp)
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{
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struct ata_drive_datas *drvp;
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int drive, s;
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u_int32_t sis_tim;
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u_int32_t idedma_ctl;
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int regtim;
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struct pciide_channel *cp = CHAN_TO_PCHAN(chp);
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struct pciide_softc *sc = CHAN_TO_PCIIDE(chp);
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sis_tim = 0;
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idedma_ctl = 0;
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/* setup DMA if needed */
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pciide_channel_dma_setup(cp);
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for (drive = 0; drive < 2; drive++) {
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regtim = SIS_TIM133(
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pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_REG_57),
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chp->ch_channel, drive);
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drvp = &chp->ch_drive[drive];
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/* If no drive, skip */
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if ((drvp->drive_flags & DRIVE) == 0)
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continue;
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/* add timing values, setup DMA if needed */
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if (drvp->drive_flags & DRIVE_UDMA) {
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/* use Ultra/DMA */
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s = splbio();
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drvp->drive_flags &= ~DRIVE_DMA;
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splx(s);
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if (pciide_pci_read(sc->sc_pc, sc->sc_tag,
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SIS96x_REG_CBL(chp->ch_channel)) & SIS96x_REG_CBL_33) {
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if (drvp->UDMA_mode > 2)
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drvp->UDMA_mode = 2;
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}
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sis_tim |= sis_udma133new_tim[drvp->UDMA_mode];
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sis_tim |= sis_pio133new_tim[drvp->PIO_mode];
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idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive);
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} else if (drvp->drive_flags & DRIVE_DMA) {
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/*
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* use Multiword DMA
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* Timings will be used for both PIO and DMA,
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* so adjust DMA mode if needed
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*/
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if (drvp->PIO_mode > (drvp->DMA_mode + 2))
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drvp->PIO_mode = drvp->DMA_mode + 2;
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if (drvp->DMA_mode + 2 > (drvp->PIO_mode))
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drvp->DMA_mode = (drvp->PIO_mode > 2) ?
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drvp->PIO_mode - 2 : 0;
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sis_tim |= sis_dma133new_tim[drvp->DMA_mode];
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idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive);
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} else {
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sis_tim |= sis_pio133new_tim[drvp->PIO_mode];
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}
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ATADEBUG_PRINT(("sis96x_setup_channel: new timings reg for "
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"channel %d drive %d: 0x%x (reg 0x%x)\n",
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chp->ch_channel, drive, sis_tim, regtim), DEBUG_PROBE);
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pci_conf_write(sc->sc_pc, sc->sc_tag, regtim, sis_tim);
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}
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if (idedma_ctl != 0) {
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/* Add software bits in status register */
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bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0,
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idedma_ctl);
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}
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}
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static void
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sis_setup_channel(struct ata_channel *chp)
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{
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struct ata_drive_datas *drvp;
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int drive, s;
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u_int32_t sis_tim;
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u_int32_t idedma_ctl;
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struct pciide_channel *cp = CHAN_TO_PCHAN(chp);
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struct pciide_softc *sc = CHAN_TO_PCIIDE(chp);
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ATADEBUG_PRINT(("sis_setup_channel: old timings reg for "
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"channel %d 0x%x\n", chp->ch_channel,
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pci_conf_read(sc->sc_pc, sc->sc_tag, SIS_TIM(chp->ch_channel))),
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DEBUG_PROBE);
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sis_tim = 0;
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idedma_ctl = 0;
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/* setup DMA if needed */
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pciide_channel_dma_setup(cp);
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for (drive = 0; drive < 2; drive++) {
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drvp = &chp->ch_drive[drive];
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/* If no drive, skip */
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if ((drvp->drive_flags & DRIVE) == 0)
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continue;
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/* add timing values, setup DMA if needed */
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if ((drvp->drive_flags & DRIVE_DMA) == 0 &&
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(drvp->drive_flags & DRIVE_UDMA) == 0)
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goto pio;
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|
|
if (drvp->drive_flags & DRIVE_UDMA) {
|
|
/* use Ultra/DMA */
|
|
s = splbio();
|
|
drvp->drive_flags &= ~DRIVE_DMA;
|
|
splx(s);
|
|
if (pciide_pci_read(sc->sc_pc, sc->sc_tag,
|
|
SIS_REG_CBL) & SIS_REG_CBL_33(chp->ch_channel)) {
|
|
if (drvp->UDMA_mode > 2)
|
|
drvp->UDMA_mode = 2;
|
|
}
|
|
switch (sc->sis_type) {
|
|
case SIS_TYPE_66:
|
|
case SIS_TYPE_100OLD:
|
|
sis_tim |= sis_udma66_tim[drvp->UDMA_mode] <<
|
|
SIS_TIM66_UDMA_TIME_OFF(drive);
|
|
break;
|
|
case SIS_TYPE_100NEW:
|
|
sis_tim |=
|
|
sis_udma100new_tim[drvp->UDMA_mode] <<
|
|
SIS_TIM100_UDMA_TIME_OFF(drive);
|
|
case SIS_TYPE_133OLD:
|
|
sis_tim |=
|
|
sis_udma133old_tim[drvp->UDMA_mode] <<
|
|
SIS_TIM100_UDMA_TIME_OFF(drive);
|
|
break;
|
|
default:
|
|
aprint_error("unknown SiS IDE type %d\n",
|
|
sc->sis_type);
|
|
}
|
|
} else {
|
|
/*
|
|
* use Multiword DMA
|
|
* Timings will be used for both PIO and DMA,
|
|
* so adjust DMA mode if needed
|
|
*/
|
|
if (drvp->PIO_mode > (drvp->DMA_mode + 2))
|
|
drvp->PIO_mode = drvp->DMA_mode + 2;
|
|
if (drvp->DMA_mode + 2 > (drvp->PIO_mode))
|
|
drvp->DMA_mode = (drvp->PIO_mode > 2) ?
|
|
drvp->PIO_mode - 2 : 0;
|
|
if (drvp->DMA_mode == 0)
|
|
drvp->PIO_mode = 0;
|
|
}
|
|
idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive);
|
|
pio: switch (sc->sis_type) {
|
|
case SIS_TYPE_NOUDMA:
|
|
case SIS_TYPE_66:
|
|
case SIS_TYPE_100OLD:
|
|
sis_tim |= sis_pio_act[drvp->PIO_mode] <<
|
|
SIS_TIM66_ACT_OFF(drive);
|
|
sis_tim |= sis_pio_rec[drvp->PIO_mode] <<
|
|
SIS_TIM66_REC_OFF(drive);
|
|
break;
|
|
case SIS_TYPE_100NEW:
|
|
case SIS_TYPE_133OLD:
|
|
sis_tim |= sis_pio_act[drvp->PIO_mode] <<
|
|
SIS_TIM100_ACT_OFF(drive);
|
|
sis_tim |= sis_pio_rec[drvp->PIO_mode] <<
|
|
SIS_TIM100_REC_OFF(drive);
|
|
break;
|
|
default:
|
|
aprint_error("unknown SiS IDE type %d\n",
|
|
sc->sis_type);
|
|
}
|
|
}
|
|
ATADEBUG_PRINT(("sis_setup_channel: new timings reg for "
|
|
"channel %d 0x%x\n", chp->ch_channel, sis_tim), DEBUG_PROBE);
|
|
pci_conf_write(sc->sc_pc, sc->sc_tag, SIS_TIM(chp->ch_channel),
|
|
sis_tim);
|
|
if (idedma_ctl != 0) {
|
|
/* Add software bits in status register */
|
|
bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0,
|
|
idedma_ctl);
|
|
}
|
|
}
|
|
|
|
static void
|
|
sis_sata_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa)
|
|
{
|
|
struct pciide_channel *cp;
|
|
pcireg_t interface = PCI_INTERFACE(pa->pa_class);
|
|
int channel;
|
|
bus_size_t cmdsize, ctlsize;
|
|
|
|
if (pciide_chipen(sc, pa) == 0)
|
|
return;
|
|
|
|
if (interface == 0) {
|
|
ATADEBUG_PRINT(("sis_sata_chip_map interface == 0\n"),
|
|
DEBUG_PROBE);
|
|
interface = PCIIDE_INTERFACE_BUS_MASTER_DMA |
|
|
PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1);
|
|
}
|
|
|
|
aprint_normal("%s: Silicon Integrated Systems 180/96X SATA controller (rev. 0x%02x)\n",
|
|
sc->sc_wdcdev.sc_atac.atac_dev.dv_xname,
|
|
PCI_REVISION(pa->pa_class));
|
|
|
|
aprint_normal("%s: bus-master DMA support present",
|
|
sc->sc_wdcdev.sc_atac.atac_dev.dv_xname);
|
|
pciide_mapreg_dma(sc, pa);
|
|
aprint_normal("\n");
|
|
|
|
if (sc->sc_dma_ok) {
|
|
sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA | ATAC_CAP_DMA;
|
|
sc->sc_wdcdev.irqack = pciide_irqack;
|
|
}
|
|
sc->sc_wdcdev.sc_atac.atac_pio_cap = 4;
|
|
sc->sc_wdcdev.sc_atac.atac_dma_cap = 2;
|
|
sc->sc_wdcdev.sc_atac.atac_udma_cap = 6;
|
|
|
|
sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray;
|
|
sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS;
|
|
sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32;
|
|
sc->sc_wdcdev.sc_atac.atac_set_modes = sata_setup_channel;
|
|
|
|
wdc_allocate_regs(&sc->sc_wdcdev);
|
|
|
|
for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels;
|
|
channel++) {
|
|
cp = &sc->pciide_channels[channel];
|
|
if (pciide_chansetup(sc, channel, interface) == 0)
|
|
continue;
|
|
pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize,
|
|
pciide_pci_intr);
|
|
}
|
|
}
|