509a188649
in the FREENIX track.
80 lines
3.1 KiB
Plaintext
80 lines
3.1 KiB
Plaintext
# $NetBSD: figure3.fig,v 1.1 1998/07/15 00:34:55 thorpej Exp $
|
|
#
|
|
# Copyright (c) 1998 Jason R. Thorpe.
|
|
# All rights reserved.
|
|
#
|
|
# Redistribution and use in source and binary forms, with or without
|
|
# modification, are permitted provided that the following conditions
|
|
# are met:
|
|
# 1. Redistributions of source code must retain the above copyright
|
|
# notice, this list of conditions and the following disclaimer.
|
|
# 2. Redistributions in binary form must reproduce the above copyright
|
|
# notice, this list of conditions and the following disclaimer in the
|
|
# documentation and/or other materials provided with the distribution.
|
|
# 3. All advertising materials mentioning features or use of this software
|
|
# must display the following acknowledgements:
|
|
# This product includes software developed for the NetBSD Project
|
|
# by Jason R. Thorpe.
|
|
# 4. The name of the author may not be used to endorse or promote products
|
|
# derived from this software without specific prior written permission.
|
|
#
|
|
# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
|
|
# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
|
|
# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
|
# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
|
|
# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
|
# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
|
# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
|
# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
|
# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
|
# OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
|
# SUCH DAMAGE.
|
|
#
|
|
#FIG 3.2
|
|
Landscape
|
|
Center
|
|
Inches
|
|
Letter
|
|
100.00
|
|
Single
|
|
-2
|
|
1200 2
|
|
2 1 0 1 0 7 0 0 -1 0.000 0 0 -1 0 0 2
|
|
1200 1200 1200 3600
|
|
2 1 0 1 0 7 0 0 -1 0.000 0 0 -1 0 0 2
|
|
1800 1200 1800 3600
|
|
2 2 0 1 0 7 0 0 10 0.000 0 0 -1 0 0 5
|
|
1200 1800 1800 1800 1800 2100 1200 2100 1200 1800
|
|
2 1 0 1 0 7 0 0 10 0.000 0 0 -1 0 0 2
|
|
2700 1200 2700 3600
|
|
2 1 0 1 0 7 0 0 10 0.000 0 0 -1 0 0 2
|
|
3300 1200 3300 3600
|
|
2 2 0 1 0 7 0 0 10 0.000 0 0 -1 0 0 5
|
|
2700 1500 3300 1500 3300 1575 2700 1575 2700 1500
|
|
2 2 0 1 0 7 0 0 10 0.000 0 0 -1 0 0 5
|
|
2700 3300 3300 3300 3300 3225 2700 3225 2700 3300
|
|
2 1 0 1 0 7 0 0 10 0.000 0 0 -1 0 0 2
|
|
2400 2100 2700 1500
|
|
2 1 0 1 0 7 0 0 10 0.000 0 0 -1 0 0 2
|
|
2400 2175 2700 1575
|
|
2 1 0 1 0 7 0 0 10 0.000 0 0 -1 0 0 2
|
|
2400 2325 2700 3225
|
|
2 1 0 1 0 7 0 0 10 0.000 0 0 -1 0 0 2
|
|
2400 2400 2700 3300
|
|
2 1 0 1 0 7 0 0 10 0.000 0 0 -1 0 0 2
|
|
1800 1800 2100 2100
|
|
2 1 0 1 0 7 0 0 10 0.000 0 0 -1 0 0 2
|
|
1800 2100 2100 2400
|
|
2 2 0 1 0 7 0 0 10 0.000 0 0 -1 0 0 5
|
|
2700 2175 3300 2175 3300 2325 2700 2325 2700 2175
|
|
2 1 0 1 0 7 0 0 -1 0.000 0 0 -1 0 0 2
|
|
2400 2175 2700 2175
|
|
2 1 0 1 0 7 0 0 -1 0.000 0 0 -1 0 0 2
|
|
2400 2325 2700 2325
|
|
2 2 0 1 0 7 0 0 51 0.000 0 0 -1 0 0 5
|
|
2100 2100 2400 2100 2400 2400 2100 2400 2100 2100
|
|
4 0 0 0 0 0 12 0.0000 4 135 1080 975 1050 DMA address\001
|
|
4 0 0 0 0 0 12 0.0000 4 135 1020 2475 1050 Host address\001
|
|
4 0 0 0 0 0 12 0.0000 4 135 465 1875 2625 MMU\001
|
|
4 0 0 0 0 0 12 0.0000 4 180 3045 825 3975 Figure 3 - scatter-gather mapped DMA\001
|