375 lines
9.9 KiB
C
375 lines
9.9 KiB
C
/* $NetBSD: agp_intel.c,v 1.11 2003/07/06 12:39:41 tron Exp $ */
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/*-
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* Copyright (c) 2000 Doug Rabson
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD: src/sys/pci/agp_intel.c,v 1.4 2001/07/05 21:28:47 jhb Exp $
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: agp_intel.c,v 1.11 2003/07/06 12:39:41 tron Exp $");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/malloc.h>
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#include <sys/kernel.h>
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#include <sys/lock.h>
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#include <sys/proc.h>
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#include <sys/agpio.h>
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#include <sys/device.h>
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#include <sys/agpio.h>
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#include <uvm/uvm_extern.h>
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#include <dev/pci/pcivar.h>
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#include <dev/pci/pcireg.h>
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#include <dev/pci/pcidevs.h>
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#include <dev/pci/agpvar.h>
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#include <dev/pci/agpreg.h>
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#include <machine/bus.h>
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struct agp_intel_softc {
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u_int32_t initial_aperture;
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/* aperture size at startup */
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struct agp_gatt *gatt;
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struct pci_attach_args vga_pa;
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u_int aperture_mask;
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int chiptype; /* Chip type */
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#define CHIP_INTEL 0x0
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#define CHIP_I443 0x1
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#define CHIP_I840 0x2
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#define CHIP_I845 0x3
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#define CHIP_I850 0x4
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};
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static u_int32_t agp_intel_get_aperture(struct agp_softc *);
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static int agp_intel_set_aperture(struct agp_softc *, u_int32_t);
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static int agp_intel_bind_page(struct agp_softc *, off_t, bus_addr_t);
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static int agp_intel_unbind_page(struct agp_softc *, off_t);
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static void agp_intel_flush_tlb(struct agp_softc *);
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struct agp_methods agp_intel_methods = {
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agp_intel_get_aperture,
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agp_intel_set_aperture,
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agp_intel_bind_page,
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agp_intel_unbind_page,
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agp_intel_flush_tlb,
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agp_generic_enable,
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agp_generic_alloc_memory,
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agp_generic_free_memory,
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agp_generic_bind_memory,
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agp_generic_unbind_memory,
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};
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static int
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agp_intel_vgamatch(struct pci_attach_args *pa)
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{
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switch (PCI_PRODUCT(pa->pa_id)) {
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case PCI_PRODUCT_INTEL_82855PM_AGP:
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case PCI_PRODUCT_INTEL_82443LX_AGP:
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case PCI_PRODUCT_INTEL_82443BX_AGP:
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case PCI_PRODUCT_INTEL_82443GX_AGP:
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case PCI_PRODUCT_INTEL_82850_AGP: /* i850/i860 */
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case PCI_PRODUCT_INTEL_82845_AGP:
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case PCI_PRODUCT_INTEL_82840_AGP:
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case PCI_PRODUCT_INTEL_82865_AGP:
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case PCI_PRODUCT_INTEL_82875P_AGP:
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return (1);
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}
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return (0);
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}
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int
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agp_intel_attach(struct device *parent, struct device *self, void *aux)
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{
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struct agp_softc *sc = (struct agp_softc *)self;
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struct pci_attach_args *pa= aux;
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struct agp_intel_softc *isc;
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struct agp_gatt *gatt;
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pcireg_t reg;
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u_int32_t value;
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isc = malloc(sizeof *isc, M_AGP, M_NOWAIT|M_ZERO);
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if (isc == NULL) {
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aprint_error(": can't allocate chipset-specific softc\n");
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return ENOMEM;
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}
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sc->as_methods = &agp_intel_methods;
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sc->as_chipc = isc;
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if (pci_find_device(&isc->vga_pa, agp_intel_vgamatch) == 0) {
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aprint_normal(": using generic initialization for Intel AGP\n");
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isc->chiptype = CHIP_INTEL;
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}
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pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_AGP, &sc->as_capoff,
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NULL);
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if (agp_map_aperture(pa, sc) != 0) {
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aprint_error(": can't map aperture\n");
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free(isc, M_AGP);
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sc->as_chipc = NULL;
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return ENXIO;
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}
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switch (PCI_PRODUCT(isc->vga_pa.pa_id)) {
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case PCI_PRODUCT_INTEL_82855PM_AGP:
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case PCI_PRODUCT_INTEL_82845_AGP:
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case PCI_PRODUCT_INTEL_82865_AGP:
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case PCI_PRODUCT_INTEL_82875P_AGP:
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isc->chiptype = CHIP_I845;
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break;
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case PCI_PRODUCT_INTEL_82840_AGP:
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isc->chiptype = CHIP_I840;
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break;
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case PCI_PRODUCT_INTEL_82850_AGP:
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isc->chiptype = CHIP_I850;
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break;
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case PCI_PRODUCT_INTEL_82443LX_AGP:
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case PCI_PRODUCT_INTEL_82443BX_AGP:
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case PCI_PRODUCT_INTEL_82443GX_AGP:
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isc->chiptype = CHIP_I443;
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break;
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}
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/* Determine maximum supported aperture size. */
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value = pci_conf_read(sc->as_pc, sc->as_tag, AGP_INTEL_APSIZE);
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pci_conf_write(sc->as_pc, sc->as_tag,
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AGP_INTEL_APSIZE, APSIZE_MASK);
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isc->aperture_mask = pci_conf_read(sc->as_pc, sc->as_tag,
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AGP_INTEL_APSIZE) & APSIZE_MASK;
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pci_conf_write(sc->as_pc, sc->as_tag, AGP_INTEL_APSIZE, value);
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isc->initial_aperture = AGP_GET_APERTURE(sc);
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for (;;) {
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gatt = agp_alloc_gatt(sc);
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if (gatt)
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break;
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/*
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* Probably contigmalloc failure. Try reducing the
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* aperture so that the gatt size reduces.
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*/
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if (AGP_SET_APERTURE(sc, AGP_GET_APERTURE(sc) / 2)) {
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agp_generic_detach(sc);
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aprint_error(": failed to set aperture\n");
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return ENOMEM;
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}
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}
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isc->gatt = gatt;
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/* Install the gatt. */
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pci_conf_write(sc->as_pc, sc->as_tag, AGP_INTEL_ATTBASE,
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gatt->ag_physical);
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/* Enable the GLTB and setup the control register. */
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switch (isc->chiptype) {
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case CHIP_I443:
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pci_conf_write(sc->as_pc, sc->as_tag, AGP_INTEL_AGPCTRL,
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AGPCTRL_AGPRSE | AGPCTRL_GTLB);
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default:
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pci_conf_write(sc->as_pc, sc->as_tag, AGP_INTEL_AGPCTRL,
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pci_conf_read(sc->as_pc, sc->as_tag, AGP_INTEL_AGPCTRL)
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| AGPCTRL_GTLB);
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}
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/* Enable things, clear errors etc. */
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switch (isc->chiptype) {
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case CHIP_I845:
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{
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pci_conf_write(sc->as_pc, sc->as_tag, AGP_INTEL_AGPCMD,
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AGPCMD_SBA | AGPCMD_AGPEN | AGPCMD_RATE_4X);
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pci_conf_write(sc->as_pc, sc->as_tag, AGP_I845_AGPMISC, AGPMISC_AAGN);
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break;
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}
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case CHIP_I840:
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case CHIP_I850:
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{
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reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_INTEL_AGPCMD);
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reg |= AGPCMD_AGPEN;
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pci_conf_write(sc->as_pc, sc->as_tag, AGP_INTEL_AGPCMD,
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reg);
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reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I840_MCHCFG);
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reg |= MCHCFG_AAGN;
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pci_conf_write(sc->as_pc, sc->as_tag, AGP_I840_MCHCFG,
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reg);
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break;
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}
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default:
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{
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reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_INTEL_NBXCFG);
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reg &= ~NBXCFG_APAE;
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reg |= NBXCFG_AAGN;
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pci_conf_write(sc->as_pc, sc->as_tag, AGP_INTEL_NBXCFG, reg);
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}
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}
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/* Clear Error status */
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switch (isc->chiptype) {
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case CHIP_I840:
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pci_conf_write(sc->as_pc, sc->as_tag,
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AGP_INTEL_I8XX_ERRSTS, 0xc000);
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break;
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case CHIP_I850:
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case CHIP_I845:
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pci_conf_write(sc->as_pc, sc->as_tag,
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AGP_INTEL_I8XX_ERRSTS, 0x00ff);
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break;
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default:
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pci_conf_write(sc->as_pc, sc->as_tag,
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AGP_INTEL_ERRSTS, 0x70);
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}
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return (0);
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}
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#if 0
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static int
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agp_intel_detach(struct agp_softc *sc)
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{
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int error;
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pcireg_t reg;
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struct agp_intel_softc *isc = sc->as_chipc;
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error = agp_generic_detach(sc);
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if (error)
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return error;
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/* XXX i845/i855PM/i840/i850E */
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reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_INTEL_NBXCFG);
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reg &= ~(1 << 9);
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printf("%s: set NBXCFG to %x\n", __FUNCTION__, reg);
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pci_conf_write(sc->as_pc, sc->as_tag, AGP_INTEL_NBXCFG, reg);
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pci_conf_write(sc->as_pc, sc->as_tag, AGP_INTEL_ATTBASE, 0);
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AGP_SET_APERTURE(sc, isc->initial_aperture);
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agp_free_gatt(sc, isc->gatt);
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return 0;
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}
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#endif
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static u_int32_t
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agp_intel_get_aperture(struct agp_softc *sc)
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{
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struct agp_intel_softc *isc = sc->as_chipc;
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u_int32_t apsize;
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apsize = pci_conf_read(sc->as_pc, sc->as_tag,
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AGP_INTEL_APSIZE) & isc->aperture_mask;
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/*
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* The size is determined by the number of low bits of
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* register APBASE which are forced to zero. The low 22 bits
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* are always forced to zero and each zero bit in the apsize
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* field just read forces the corresponding bit in the 27:22
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* to be zero. We calculate the aperture size accordingly.
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*/
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return (((apsize ^ isc->aperture_mask) << 22) | ((1 << 22) - 1)) + 1;
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}
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static int
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agp_intel_set_aperture(struct agp_softc *sc, u_int32_t aperture)
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{
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struct agp_intel_softc *isc = sc->as_chipc;
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u_int32_t apsize;
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/*
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* Reverse the magic from get_aperture.
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*/
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apsize = ((aperture - 1) >> 22) ^ isc->aperture_mask;
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/*
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* Double check for sanity.
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*/
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if ((((apsize ^ isc->aperture_mask) << 22) |
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((1 << 22) - 1)) + 1 != aperture)
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return EINVAL;
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pci_conf_write(sc->as_pc, sc->as_tag,
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AGP_INTEL_APSIZE, apsize);
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return 0;
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}
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static int
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agp_intel_bind_page(struct agp_softc *sc, off_t offset, bus_addr_t physical)
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{
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struct agp_intel_softc *isc = sc->as_chipc;
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if (offset < 0 || offset >= (isc->gatt->ag_entries << AGP_PAGE_SHIFT))
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return EINVAL;
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isc->gatt->ag_virtual[offset >> AGP_PAGE_SHIFT] = physical | 0x17;
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return 0;
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}
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static int
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agp_intel_unbind_page(struct agp_softc *sc, off_t offset)
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{
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struct agp_intel_softc *isc = sc->as_chipc;
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if (offset < 0 || offset >= (isc->gatt->ag_entries << AGP_PAGE_SHIFT))
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return EINVAL;
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isc->gatt->ag_virtual[offset >> AGP_PAGE_SHIFT] = 0;
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return 0;
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}
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static void
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agp_intel_flush_tlb(struct agp_softc *sc)
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{
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struct agp_intel_softc *isc = sc->as_chipc;
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pcireg_t reg;
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switch (isc->chiptype) {
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case CHIP_I850:
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case CHIP_I845:
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case CHIP_I840:
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case CHIP_I443:
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{
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reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_INTEL_AGPCTRL);
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reg &= ~AGPCTRL_GTLB;
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pci_conf_write(sc->as_pc, sc->as_tag, AGP_INTEL_AGPCTRL,
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reg);
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pci_conf_write(sc->as_pc, sc->as_tag, AGP_INTEL_AGPCTRL,
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reg | AGPCTRL_GTLB);
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break;
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}
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default: /* XXX */
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{
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pci_conf_write(sc->as_pc, sc->as_tag, AGP_INTEL_AGPCTRL,
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0x2200);
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pci_conf_write(sc->as_pc, sc->as_tag, AGP_INTEL_AGPCTRL,
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0x2280);
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}
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}
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}
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