130 lines
5.3 KiB
C
130 lines
5.3 KiB
C
/* $NetBSD: sireg.h,v 1.3 2008/04/28 20:24:01 martin Exp $ */
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/*-
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* Copyright (c) 2000 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Paul Kranenburg.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Register map for the VME SCSI-3 adpater (si)
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* The first part of this register map is an NCR5380
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* SCSI Bus Interface Controller (SBIC). The rest is a
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* DMA controller and custom logic.
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*/
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#if __for_reference_only__
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/*
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* Am5380 Register map (no padding). See dev/ic/ncr5380reg.h
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*/
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struct ncr5380regs {
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u_char r[8];
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};
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struct si_regs {
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struct ncr5380regs sci;
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/* DMA controller registers */
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u_short dma_addrh; /* DMA address (VME only) */
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u_short dma_addrl; /* (high word, low word) */
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u_short dma_counth; /* DMA count (VME only) */
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u_short dma_countl; /* (high word, low word) */
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u_int pad0; /* no-existent register */
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u_short fifo_data; /* fifo data register */
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u_short fifo_count; /* fifo count register */
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u_short si_csr; /* si control/status */
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u_short bprh; /* VME byte pack high */
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u_short bprl; /* VME byte pack low */
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u_short iv_am; /* bits 0-7: intr vector */
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/* bits 8-13: addr modifier (VME only) */
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/* bits 14-15: unused */
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u_short fifo_cnt_hi; /* high part of fifo_count (VME only) */
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/* Whole thing repeats after 32 bytes. */
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u_short _space[3];
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};
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#endif
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/*
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* Size of NCR5380 registers located at the bottom of the register bank
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*/
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#define NCR5380REGS_SZ 8
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/*
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* Register definition for the `si' VME controller
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*/
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#define SIREG_DMA_ADDRH (NCR5380REGS_SZ + 0) /* DMA address, high word */
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#define SIREG_DMA_ADDRL (NCR5380REGS_SZ + 2) /* DMA address, low word */
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#define SIREG_DMA_CNTH (NCR5380REGS_SZ + 4) /* DMA count, high word */
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#define SIREG_DMA_CNTL (NCR5380REGS_SZ + 6) /* DMA count, low word */
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#define SIREG_FIFO_DATA (NCR5380REGS_SZ + 12) /* FIFO data */
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#define SIREG_FIFO_CNT (NCR5380REGS_SZ + 14) /* FIFO count, low word */
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#define SIREG_CSR (NCR5380REGS_SZ + 16) /* Control/status register */
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#define SIREG_BPRH (NCR5380REGS_SZ + 18) /* VME byte pack, high word */
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#define SIREG_BPRL (NCR5380REGS_SZ + 20) /* VME byte pack, low word */
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#define SIREG_IV_AM (NCR5380REGS_SZ + 22) /* bits 0-7: intr vector;
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bits 8-13: addr modifier */
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#define SIREG_FIFO_CNTH (NCR5380REGS_SZ + 24) /* FIFO count, high word */
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#define SIREG_BANK_SZ (NCR5380REGS_SZ + 26)
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/*
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* Status Register.
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* Note:
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* (r) indicates bit is read only.
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* (rw) indicates bit is read or write.
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* (v) vme host adaptor interface only.
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* (o) sun3/50 onboard host adaptor interface only.
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* (b) both vme and sun3/50 host adaptor interfaces.
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*
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* Note 2: because of the historical connections of this VME driver
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* with the on-board SCSI interfaces found in sun3/50, sun3/60 and sun4/100
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* systems, the (v), (o) and (b) qualifications are left in for
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* cross-reference.
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*/
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#define SI_CSR_DMA_ACTIVE 0x8000 /* (r,o) DMA transfer active */
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#define SI_CSR_DMA_CONFLICT 0x4000 /* (r,b) reg accessed while DMA'ing */
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#define SI_CSR_DMA_BUS_ERR 0x2000 /* (r,b) bus error during DMA */
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#define SI_CSR_ID 0x1000 /* (r,b) 0 for 3/50, 1 for SCSI-3, */
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/* 0 if SCSI-3 unmodified */
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#define SI_CSR_FIFO_FULL 0x0800 /* (r,b) fifo full */
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#define SI_CSR_FIFO_EMPTY 0x0400 /* (r,b) fifo empty */
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#define SI_CSR_SBC_IP 0x0200 /* (r,b) sbc interrupt pending */
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#define SI_CSR_DMA_IP 0x0100 /* (r,b) DMA interrupt pending */
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#define SI_CSR_LOB 0x00c0 /* (r,v) number of leftover bytes */
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#define SI_CSR_LOB_THREE 0x00c0 /* (r,v) three leftover bytes */
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#define SI_CSR_LOB_TWO 0x0080 /* (r,v) two leftover bytes */
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#define SI_CSR_LOB_ONE 0x0040 /* (r,v) one leftover byte */
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#define SI_CSR_BPCON 0x0020 /* (rw,v) byte packing control */
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/* DMA is in 0=longwords, 1=words */
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#define SI_CSR_DMA_EN 0x0010 /* (rw,v) DMA/interrupt enable */
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#define SI_CSR_SEND 0x0008 /* (rw,b) DMA dir, 1=to device */
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#define SI_CSR_INTR_EN 0x0004 /* (rw,b) interrupts enable */
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#define SI_CSR_FIFO_RES 0x0002 /* (rw,b) inits fifo, 0=reset */
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#define SI_CSR_SCSI_RES 0x0001 /* (rw,b) reset sbc and udc, 0=reset */
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