183 lines
6.3 KiB
C
183 lines
6.3 KiB
C
/* $NetBSD: ncr5380reg.h,v 1.1.1.1 1995/03/26 07:12:15 leo Exp $ */
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/*
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* Copyright (c) 1995 Leo Weppelman.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Leo Weppelman.
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* 4. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _NCR5380REG_H
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#define _NCR5380REG_H
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/*
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* Atari TT hardware:
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* SCSI interface + DMA.
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* The SCSI chip is an NCR5380
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*/
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#define SCSI_DMA ((struct scsi_dma *)AD_SCSI_DMA)
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#define SCSI_5380 ((struct scsi_5380 *)AD_NCR5380)
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struct scsi_dma {
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volatile u_char s_dma_ptr[8]; /* use only the odd bytes */
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volatile u_char s_dma_cnt[8]; /* use only the odd bytes */
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volatile u_char s_dma_res[4]; /* data residue register */
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volatile u_char s_dma_gap; /* not used */
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volatile u_char s_dma_ctrl; /* control register */
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};
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#define set_scsi_dma(addr, val) (void)( \
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{ \
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u_char *address = (u_char*)addr+1; \
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u_long nval = (u_long)val; \
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__asm("movepl %0, %1@(0)": :"d" (nval), "a" (address)); \
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})
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#define get_scsi_dma(addr, res) ( \
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{ \
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u_char *address = (u_char*)addr+1; \
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u_long nval; \
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__asm("movepl %1@(0), %0": "=d" (nval) : "a" (address)); \
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res = (u_long)nval; \
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})
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/*
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* Defines for DMA control register
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*/
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#define SD_BUSERR 0x80 /* 1 = transfer caused bus error*/
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#define SD_ZERO 0x40 /* 1 = byte counter is zero */
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#define SD_ENABLE 0x02 /* 1 = Enable DMA */
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#define SD_OUT 0x01 /* Direction: memory to SCSI */
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#define SD_IN 0x00 /* Direction: SCSI to memory */
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struct scsi_5380 {
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volatile u_char scsi_5380[16]; /* use only the odd bytes */
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};
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#define scsi_data scsi_5380[ 1] /* Data register */
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#define scsi_icom scsi_5380[ 3] /* Initiator command register */
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#define scsi_mode scsi_5380[ 5] /* Mode register */
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#define scsi_tcom scsi_5380[ 7] /* Target command register */
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#define scsi_idstat scsi_5380[ 9] /* Bus status register */
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#define scsi_dmstat scsi_5380[11] /* DMA status register */
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#define scsi_trcv scsi_5380[13] /* Target receive register */
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#define scsi_ircv scsi_5380[15] /* Initiator receive register */
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/*
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* Definitions for Initiator command register.
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*/
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#define SC_A_RST 0x80 /* RW - Assert RST */
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#define SC_TEST 0x40 /* W - Test mode */
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#define SC_AIP 0x40 /* R - Arbitration in progress */
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#define SC_LA 0x20 /* R - Lost arbitration */
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#define SC_A_ACK 0x10 /* RW - Assert ACK */
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#define SC_A_BSY 0x08 /* RW - Assert BSY */
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#define SC_A_SEL 0x04 /* RW - Assert SEL */
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#define SC_A_ATN 0x02 /* RW - Assert ATN */
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#define SC_ADTB 0x01 /* RW - Assert Data To Bus */
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/*
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* Definitions for mode register
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*/
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#define SC_B_DMA 0x80 /* RW - Block mode DMA (not on TT!) */
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#define SC_T_MODE 0x40 /* RW - Target mode */
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#define SC_E_PAR 0x20 /* RW - Enable parity check */
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#define SC_E_PARI 0x10 /* RW - Enable parity interrupt */
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#define SC_E_EOPI 0x08 /* RW - Enable End Of Process Interrupt */
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#define SC_MON_BSY 0x04 /* RW - Monitor BSY */
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#define SC_M_DMA 0x02 /* RW - Set DMA mode */
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#define SC_ARBIT 0x01 /* RW - Arbitrate */
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/*
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* Definitions for tcom register
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*/
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#define SC_LBS 0x80 /* RW - Last Byte Send (not on TT!) */
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#define SC_A_REQ 0x08 /* RW - Assert REQ */
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#define SC_A_MSG 0x04 /* RW - Assert MSG */
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#define SC_A_CD 0x02 /* RW - Assert C/D */
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#define SC_A_IO 0x01 /* RW - Assert I/O */
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/*
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* Definitions for idstat register
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*/
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#define SC_S_RST 0x80 /* R - RST is set */
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#define SC_S_BSY 0x40 /* R - BSY is set */
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#define SC_S_REQ 0x20 /* R - REQ is set */
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#define SC_S_MSG 0x10 /* R - MSG is set */
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#define SC_S_CD 0x08 /* R - C/D is set */
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#define SC_S_IO 0x04 /* R - I/O is set */
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#define SC_S_SEL 0x02 /* R - SEL is set */
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#define SC_S_PAR 0x01 /* R - Parity bit */
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/*
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* Definitions for dmastat register
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*/
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#define SC_END_DMA 0x80 /* R - End of DMA */
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#define SC_DMA_REQ 0x40 /* R - DMA request */
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#define SC_PAR_ERR 0x20 /* R - Parity error */
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#define SC_IRQ_SET 0x10 /* R - IRQ is active */
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#define SC_PHS_MTCH 0x08 /* R - Phase Match */
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#define SC_BSY_ERR 0x04 /* R - Busy error */
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#define SC_ATN_STAT 0x02 /* R - State of ATN line */
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#define SC_ACK_STAT 0x01 /* R - State of ACK line */
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#define SC_S_SEND 0x00 /* W - Start DMA output */
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#define SC_CLINT { /* Clear interrupts */ \
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int i = SCSI_5380->scsi_ircv; \
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}
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/*
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* Definition of SCSI-bus phases. The values are determined by signals
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* on the SCSI-bus. DO NOT CHANGE!
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* The values must be used to index the pointers in SCSI-PARMS.
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*/
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#define NR_PHASE 8
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#define PH_DATAOUT 0
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#define PH_DATAIN 1
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#define PH_CMD 2
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#define PH_STATUS 3
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#define PH_RES1 4
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#define PH_RES2 5
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#define PH_MSGOUT 6
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#define PH_MSGIN 7
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#define PH_OUT(phase) (!(phase & 1)) /* TRUE if output phase */
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#define PH_IN(phase) (phase & 1) /* TRUE if input phase */
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/*
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* Id of Host-adapter
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*/
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#define SC_HOST_ID 0x80
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/*
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* Base setting for 5380 mode register
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*/
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#define IMODE_BASE SC_E_PAR
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#endif /* _NCR5380REG_H */
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