497 lines
13 KiB
C
497 lines
13 KiB
C
/* This file is part of the program psim.
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Copyright (C) 1994-1997, Andrew Cagney <cagney@highland.com.au>
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Copyright (C) 1996, 1997, Free Software Foundation
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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*/
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#ifndef ENGINE_C
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#define ENGINE_C
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#include "sim-main.h"
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#include <stdio.h>
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#include <ctype.h>
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#ifdef HAVE_STDLIB_H
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#include <stdlib.h>
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#endif
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#ifdef HAVE_STRING_H
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#include <string.h>
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#else
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#ifdef HAVE_STRINGS_H
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#include <strings.h>
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#endif
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#endif
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static void
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do_stack_swap (SIM_DESC sd)
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{
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sim_cpu *cpu = STATE_CPU (sd, 0);
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unsigned new_sp = (PSW_VAL(PSW_SM) != 0);
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if (cpu->regs.current_sp != new_sp)
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{
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cpu->regs.sp[cpu->regs.current_sp] = SP;
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cpu->regs.current_sp = new_sp;
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SP = cpu->regs.sp[cpu->regs.current_sp];
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}
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}
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#if WITH_TRACE
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/* Implement ALU tracing of 32-bit registers. */
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static void
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trace_alu32 (SIM_DESC sd,
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sim_cpu *cpu,
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address_word cia,
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unsigned32 *ptr)
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{
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unsigned32 value = *ptr;
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if (ptr >= &GPR[0] && ptr <= &GPR[NR_GENERAL_PURPOSE_REGISTERS])
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trace_one_insn (sd, cpu, cia, 1, "engine.c", __LINE__, "alu",
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"Set register r%-2d = 0x%.8lx (%ld)",
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ptr - &GPR[0], (long)value, (long)value);
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else if (ptr == &PSW || ptr == &bPSW || ptr == &DPSW)
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trace_one_insn (sd, cpu, cia, 1, "engine.c", __LINE__, "alu",
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"Set register %s = 0x%.8lx%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s",
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(ptr == &PSW) ? "psw" : ((ptr == &bPSW) ? "bpsw" : "dpsw"),
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(long)value,
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(value & (0x80000000 >> PSW_SM)) ? ", sm" : "",
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(value & (0x80000000 >> PSW_EA)) ? ", ea" : "",
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(value & (0x80000000 >> PSW_DB)) ? ", db" : "",
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(value & (0x80000000 >> PSW_DS)) ? ", ds" : "",
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(value & (0x80000000 >> PSW_IE)) ? ", ie" : "",
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(value & (0x80000000 >> PSW_RP)) ? ", rp" : "",
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(value & (0x80000000 >> PSW_MD)) ? ", md" : "",
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(value & (0x80000000 >> PSW_F0)) ? ", f0" : "",
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(value & (0x80000000 >> PSW_F1)) ? ", f1" : "",
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(value & (0x80000000 >> PSW_F2)) ? ", f2" : "",
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(value & (0x80000000 >> PSW_F3)) ? ", f3" : "",
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(value & (0x80000000 >> PSW_S)) ? ", s" : "",
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(value & (0x80000000 >> PSW_V)) ? ", v" : "",
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(value & (0x80000000 >> PSW_VA)) ? ", va" : "",
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(value & (0x80000000 >> PSW_C)) ? ", c" : "");
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else if (ptr >= &CREG[0] && ptr <= &CREG[NR_CONTROL_REGISTERS])
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trace_one_insn (sd, cpu, cia, 1, "engine.c", __LINE__, "alu",
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"Set register cr%d = 0x%.8lx (%ld)",
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ptr - &CREG[0], (long)value, (long)value);
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}
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/* Implement ALU tracing of 32-bit registers. */
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static void
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trace_alu64 (SIM_DESC sd,
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sim_cpu *cpu,
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address_word cia,
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unsigned64 *ptr)
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{
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unsigned64 value = *ptr;
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if (ptr >= &ACC[0] && ptr <= &ACC[NR_ACCUMULATORS])
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trace_one_insn (sd, cpu, cia, 1, "engine.c", __LINE__, "alu",
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"Set register a%-2d = 0x%.8lx 0x%.8lx",
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ptr - &ACC[0],
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(unsigned long)(unsigned32)(value >> 32),
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(unsigned long)(unsigned32)value);
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}
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#endif
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/* Process all of the queued up writes in order now */
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void
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unqueue_writes (SIM_DESC sd,
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sim_cpu *cpu,
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address_word cia)
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{
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int i, num;
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int did_psw = 0;
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unsigned32 *psw_addr = &PSW;
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num = WRITE32_NUM;
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for (i = 0; i < num; i++)
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{
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unsigned32 mask = WRITE32_MASK (i);
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unsigned32 *ptr = WRITE32_PTR (i);
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unsigned32 value = (*ptr & ~mask) | (WRITE32_VALUE (i) & mask);
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int j;
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if (ptr == psw_addr)
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{
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/* If MU instruction was not a MVTSYS, resolve PSW
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contention in favour of IU. */
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if(! STATE_CPU (sd, 0)->mvtsys_left_p)
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{
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/* Detect contention in parallel writes to the same PSW flags.
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The hardware allows the updates from IU to prevail over
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those from MU. */
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unsigned32 flag_bits =
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BIT32 (PSW_F0) | BIT32 (PSW_F1) |
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BIT32 (PSW_F2) | BIT32 (PSW_F3) |
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BIT32 (PSW_S) | BIT32 (PSW_V) |
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BIT32 (PSW_VA) | BIT32 (PSW_C);
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unsigned32 my_flag_bits = mask & flag_bits;
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for (j = i + 1; j < num; j++)
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if (WRITE32_PTR (j) == psw_addr && /* write to PSW */
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WRITE32_MASK (j) & my_flag_bits) /* some of the same flags */
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{
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/* Recompute local mask & value, to suppress this
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earlier write to the same flag bits. */
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unsigned32 new_mask = mask & ~(WRITE32_MASK (j) & my_flag_bits);
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/* There is a special case for the VA (accumulated
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overflow) flag, in that it is only included in the
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second instruction's mask if the overflow
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occurred. Yet the hardware still suppresses the
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first instruction's update to VA. So we kludge
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this by inferring PSW_V -> PSW_VA for the second
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instruction. */
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if (WRITE32_MASK (j) & BIT32 (PSW_V))
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{
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new_mask &= ~BIT32 (PSW_VA);
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}
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value = (*ptr & ~new_mask) | (WRITE32_VALUE (i) & new_mask);
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}
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}
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did_psw = 1;
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}
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*ptr = value;
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#if WITH_TRACE
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if (TRACE_ALU_P (cpu))
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trace_alu32 (sd, cpu, cia, ptr);
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#endif
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}
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num = WRITE64_NUM;
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for (i = 0; i < num; i++)
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{
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unsigned64 *ptr = WRITE64_PTR (i);
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*ptr = WRITE64_VALUE (i);
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#if WITH_TRACE
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if (TRACE_ALU_P (cpu))
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trace_alu64 (sd, cpu, cia, ptr);
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#endif
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}
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WRITE32_NUM = 0;
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WRITE64_NUM = 0;
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if (DID_TRAP == 1) /* ordinary trap */
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{
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bPSW = PSW;
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PSW &= (BIT32 (PSW_DB) | BIT32 (PSW_SM));
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did_psw = 1;
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}
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else if (DID_TRAP == 2) /* debug trap */
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{
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DPSW = PSW;
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PSW &= BIT32 (PSW_DS);
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PSW |= BIT32 (PSW_DS);
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did_psw = 1;
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}
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DID_TRAP = 0;
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if (did_psw)
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do_stack_swap (sd);
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}
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/* SIMULATE INSTRUCTIONS, various different ways of achieving the same
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thing */
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static address_word
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do_long (SIM_DESC sd,
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l_instruction_word instruction,
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address_word cia)
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{
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address_word nia = l_idecode_issue(sd,
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instruction,
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cia);
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unqueue_writes (sd, STATE_CPU (sd, 0), cia);
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return nia;
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}
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static address_word
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do_2_short (SIM_DESC sd,
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s_instruction_word insn1,
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s_instruction_word insn2,
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cpu_units unit,
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address_word cia)
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{
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address_word nia;
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/* run the first instruction */
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STATE_CPU (sd, 0)->unit = unit;
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STATE_CPU (sd, 0)->left_kills_right_p = 0;
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STATE_CPU (sd, 0)->mvtsys_left_p = 0;
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nia = s_idecode_issue(sd,
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insn1,
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cia);
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unqueue_writes (sd, STATE_CPU (sd, 0), cia);
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/* Only do the second instruction if the PC has not changed */
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if ((nia == INVALID_INSTRUCTION_ADDRESS) &&
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(! STATE_CPU (sd, 0)->left_kills_right_p)) {
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STATE_CPU (sd, 0)->unit = any_unit;
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nia = s_idecode_issue (sd,
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insn2,
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cia);
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unqueue_writes (sd, STATE_CPU (sd, 0), cia);
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}
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STATE_CPU (sd, 0)->left_kills_right_p = 0;
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STATE_CPU (sd, 0)->mvtsys_left_p = 0;
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return nia;
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}
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static address_word
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do_parallel (SIM_DESC sd,
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s_instruction_word left_insn,
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s_instruction_word right_insn,
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address_word cia)
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{
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address_word nia_left;
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address_word nia_right;
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address_word nia;
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/* run the first instruction */
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STATE_CPU (sd, 0)->unit = memory_unit;
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STATE_CPU (sd, 0)->left_kills_right_p = 0;
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STATE_CPU (sd, 0)->mvtsys_left_p = 0;
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nia_left = s_idecode_issue(sd,
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left_insn,
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cia);
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/* run the second instruction */
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STATE_CPU (sd, 0)->unit = integer_unit;
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nia_right = s_idecode_issue(sd,
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right_insn,
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cia);
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/* merge the PC's */
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if (nia_left == INVALID_INSTRUCTION_ADDRESS) {
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if (nia_right == INVALID_INSTRUCTION_ADDRESS)
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nia = INVALID_INSTRUCTION_ADDRESS;
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else
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nia = nia_right;
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}
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else {
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if (nia_right == INVALID_INSTRUCTION_ADDRESS)
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nia = nia_left;
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else {
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sim_engine_abort (sd, STATE_CPU (sd, 0), cia, "parallel jumps");
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nia = INVALID_INSTRUCTION_ADDRESS;
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}
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}
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unqueue_writes (sd, STATE_CPU (sd, 0), cia);
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return nia;
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}
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typedef enum {
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p_insn = 0,
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long_insn = 3,
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l_r_insn = 1,
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r_l_insn = 2,
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} instruction_types;
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STATIC_INLINE instruction_types
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instruction_type(l_instruction_word insn)
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{
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int fm0 = MASKED64(insn, 0, 0) != 0;
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int fm1 = MASKED64(insn, 32, 32) != 0;
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return ((fm0 << 1) | fm1);
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}
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void
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sim_engine_run (SIM_DESC sd,
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int last_cpu_nr,
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int nr_cpus,
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int siggnal)
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{
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while (1)
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{
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address_word cia = PC;
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address_word nia;
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l_instruction_word insn = IMEM(cia);
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int rp_was_set;
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int rpt_c_was_nonzero;
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/* Before executing the instruction, we need to test whether or
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not RPT_C is greater than zero, and save that state for use
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after executing the instruction. In particular, we need to
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not care whether the instruction changes RPT_C itself. */
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rpt_c_was_nonzero = (RPT_C > 0);
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/* Before executing the instruction, we need to check to see if
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we have to decrement RPT_C, the repeat count register. Do this
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if PC == RPT_E, but only if we are in an active repeat block. */
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if (PC == RPT_E &&
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(RPT_C > 0 || PSW_VAL (PSW_RP) != 0))
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{
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RPT_C --;
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}
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/* Now execute the instruction at PC */
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switch (instruction_type (insn))
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{
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case long_insn:
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nia = do_long (sd, insn, cia);
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break;
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case r_l_insn:
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/* L <- R */
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nia = do_2_short (sd, insn, insn >> 32, integer_unit, cia);
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break;
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case l_r_insn:
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/* L -> R */
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nia = do_2_short (sd, insn >> 32, insn, memory_unit, cia);
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break;
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case p_insn:
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nia = do_parallel (sd, insn >> 32, insn, cia);
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break;
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default:
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sim_engine_abort (sd, STATE_CPU (sd, 0), cia,
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"internal error - engine_run_until_stop - bad switch");
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nia = -1;
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}
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if (TRACE_ACTION)
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{
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if (TRACE_ACTION & TRACE_ACTION_CALL)
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call_occurred (sd, STATE_CPU (sd, 0), cia, nia);
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if (TRACE_ACTION & TRACE_ACTION_RETURN)
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return_occurred (sd, STATE_CPU (sd, 0), cia, nia);
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TRACE_ACTION = 0;
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}
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/* Check now to see if we need to reset the RP bit in the PSW.
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There are three conditions for this, the RP bit is already
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set (just a speed optimization), the instruction we just
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executed is the last instruction in the loop, and the repeat
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count is currently zero. */
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rp_was_set = PSW_VAL (PSW_RP);
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if (rp_was_set && (PC == RPT_E) && RPT_C == 0)
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{
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PSW_SET (PSW_RP, 0);
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}
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/* Now update the PC. If we just executed a jump instruction,
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that takes precedence over everything else. Next comes
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branching back to RPT_S as a result of a loop. Finally, the
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default is to simply advance to the next inline
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instruction. */
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if (nia != INVALID_INSTRUCTION_ADDRESS)
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{
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PC = nia;
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}
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else if (rp_was_set && rpt_c_was_nonzero && (PC == RPT_E))
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{
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PC = RPT_S;
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}
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else
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{
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PC = cia + 8;
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}
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/* Check for DDBT (debugger debug trap) condition. Do this after
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the repeat block checks so the excursion to the trap handler does
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not alter looping state. */
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if (cia == IBA && PSW_VAL (PSW_DB))
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{
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DPC = PC;
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PSW_SET (PSW_EA, 1);
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DPSW = PSW;
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/* clear all bits in PSW except SM */
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PSW &= BIT32 (PSW_SM);
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/* add DS bit */
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PSW |= BIT32 (PSW_DS);
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/* dispatch to DDBT handler */
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PC = 0xfffff128; /* debugger_debug_trap_address */
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}
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/* process any events */
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/* FIXME - should L->R or L<-R insns count as two cycles? */
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if (sim_events_tick (sd))
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{
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sim_events_process (sd);
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}
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}
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}
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/* d30v external interrupt handler.
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Note: This should be replaced by a proper interrupt delivery
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mechanism. This interrupt mechanism discards later interrupts if
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an earlier interrupt hasn't been delivered.
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Note: This interrupt mechanism does not reset its self when the
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simulator is re-opened. */
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void
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d30v_interrupt_event (SIM_DESC sd,
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void *data)
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{
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if (PSW_VAL (PSW_IE))
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/* interrupts not masked */
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{
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/* scrub any pending interrupt */
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if (sd->pending_interrupt != NULL)
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sim_events_deschedule (sd, sd->pending_interrupt);
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/* deliver */
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bPSW = PSW;
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bPC = PC;
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PSW = 0;
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PC = 0xfffff138; /* external interrupt */
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do_stack_swap (sd);
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}
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else if (sd->pending_interrupt == NULL)
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/* interrupts masked and no interrupt pending */
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{
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sd->pending_interrupt = sim_events_schedule (sd, 1,
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d30v_interrupt_event,
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data);
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}
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}
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#endif
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