311 lines
7.9 KiB
ArmAsm
311 lines
7.9 KiB
ArmAsm
/* $NetBSD: cpufunc_asm_sa1.S,v 1.11 2010/01/03 04:25:16 uebayasi Exp $ */
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/*
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* Copyright (c) 1997,1998 Mark Brinicombe.
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* Copyright (c) 1997 Causality Limited
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Causality Limited.
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* 4. The name of Causality Limited may not be used to endorse or promote
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* products derived from this software without specific prior written
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* permission.
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*
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* THIS SOFTWARE IS PROVIDED BY CAUSALITY LIMITED ``AS IS'' AND ANY EXPRESS
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* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL CAUSALITY LIMITED BE LIABLE FOR ANY DIRECT,
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* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* SA-1 assembly functions for CPU / MMU / TLB specific operations
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*/
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#include <machine/cpu.h>
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#include <machine/asm.h>
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.Lblock_userspace_access:
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.word _C_LABEL(block_userspace_access)
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/*
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* Functions to set the MMU Translation Table Base register
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*
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* We need to clean and flush the cache as it uses virtual
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* addresses that are about to change.
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*/
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ENTRY(sa1_setttb)
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#ifdef CACHE_CLEAN_BLOCK_INTR
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mrs r3, cpsr_all
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orr r1, r3, #(I32_bit | F32_bit)
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msr cpsr_all, r1
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#else
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ldr r3, .Lblock_userspace_access
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ldr r2, [r3]
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orr r1, r2, #1
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str r1, [r3]
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#endif
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stmfd sp!, {r0-r3, lr}
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bl _C_LABEL(sa1_cache_cleanID)
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ldmfd sp!, {r0-r3, lr}
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mcr p15, 0, r0, c7, c5, 0 /* invalidate I$ and BTB */
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mcr p15, 0, r0, c7, c10, 4 /* drain write and fill buffer */
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/* Write the TTB */
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mcr p15, 0, r0, c2, c0, 0
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/* If we have updated the TTB we must flush the TLB */
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mcr p15, 0, r0, c8, c7, 0 /* invalidate I+D TLB */
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/* The cleanID above means we only need to flush the I cache here */
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mcr p15, 0, r0, c7, c5, 0 /* invalidate I$ and BTB */
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/* Make sure that pipeline is emptied */
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mov r0, r0
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mov r0, r0
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#ifdef CACHE_CLEAN_BLOCK_INTR
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msr cpsr_all, r3
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#else
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str r2, [r3]
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#endif
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mov pc, lr
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/*
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* TLB functions
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*/
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ENTRY(sa1_tlb_flushID_SE)
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mcr p15, 0, r0, c8, c6, 1 /* flush D tlb single entry */
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mcr p15, 0, r0, c8, c5, 0 /* flush I tlb */
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mov pc, lr
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/*
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* Cache functions
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*/
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ENTRY(sa1_cache_flushID)
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mcr p15, 0, r0, c7, c7, 0 /* flush I+D cache */
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mov pc, lr
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ENTRY(sa1_cache_flushI)
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mcr p15, 0, r0, c7, c5, 0 /* flush I cache */
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mov pc, lr
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ENTRY(sa1_cache_flushD)
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mcr p15, 0, r0, c7, c6, 0 /* flush D cache */
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mov pc, lr
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ENTRY(sa1_cache_flushD_SE)
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mcr p15, 0, r0, c7, c6, 1 /* flush D cache single entry */
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mov pc, lr
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ENTRY(sa1_cache_cleanD_E)
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mcr p15, 0, r0, c7, c10, 1 /* clean D cache entry */
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mov pc, lr
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/*
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* Information for the SA-1 cache clean/purge functions:
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*
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* * Virtual address of the memory region to use
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* * Size of memory region
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*/
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.data
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.global _C_LABEL(sa1_cache_clean_addr)
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_C_LABEL(sa1_cache_clean_addr):
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.word 0xf0000000
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.global _C_LABEL(sa1_cache_clean_size)
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_C_LABEL(sa1_cache_clean_size):
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#if defined(CPU_SA1100) || defined(CPU_SA1110)
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.word 0x00004000
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#else
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.word 0x00008000
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#endif
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.text
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.Lsa1_cache_clean_addr:
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.word _C_LABEL(sa1_cache_clean_addr)
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.Lsa1_cache_clean_size:
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.word _C_LABEL(sa1_cache_clean_size)
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#ifdef CACHE_CLEAN_BLOCK_INTR
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#define SA1_CACHE_CLEAN_BLOCK \
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mrs r3, cpsr_all ; \
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orr r0, r3, #(I32_bit | F32_bit) ; \
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msr cpsr_all, r0
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#define SA1_CACHE_CLEAN_UNBLOCK \
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msr cpsr_all, r3
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#else
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#define SA1_CACHE_CLEAN_BLOCK \
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ldr r3, .Lblock_userspace_access ; \
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ldr ip, [r3] ; \
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orr r0, ip, #1 ; \
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str r0, [r3]
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#define SA1_CACHE_CLEAN_UNBLOCK \
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str ip, [r3]
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#endif /* CACHE_CLEAN_BLOCK_INTR */
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#ifdef DOUBLE_CACHE_CLEAN_BANK
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#define SA1_DOUBLE_CACHE_CLEAN_BANK \
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eor r0, r0, r1 ; \
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str r0, [r2]
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#else
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#define SA1_DOUBLE_CACHE_CLEAN_BANK /* nothing */
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#endif /* DOUBLE_CACHE_CLEAN_BANK */
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#define SA1_CACHE_CLEAN_PROLOGUE \
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SA1_CACHE_CLEAN_BLOCK ; \
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ldr r2, .Lsa1_cache_clean_addr ; \
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ldmia r2, {r0, r1} ; \
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SA1_DOUBLE_CACHE_CLEAN_BANK
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#define SA1_CACHE_CLEAN_EPILOGUE \
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SA1_CACHE_CLEAN_UNBLOCK
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ENTRY_NP(sa1_cache_syncI)
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ENTRY_NP(sa1_cache_purgeID)
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mcr p15, 0, r0, c7, c5, 0 /* flush I cache (D cleaned below) */
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ENTRY_NP(sa1_cache_cleanID)
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ENTRY_NP(sa1_cache_purgeD)
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ENTRY(sa1_cache_cleanD)
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SA1_CACHE_CLEAN_PROLOGUE
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1: ldr r2, [r0], #32
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subs r1, r1, #32
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bne 1b
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mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */
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SA1_CACHE_CLEAN_EPILOGUE
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mov pc, lr
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ENTRY(sa1_cache_purgeID_E)
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mcr p15, 0, r0, c7, c10, 1 /* clean dcache entry */
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mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */
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mcr p15, 0, r0, c7, c5, 0 /* flush I cache */
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mcr p15, 0, r0, c7, c6, 1 /* flush D cache single entry */
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mov pc, lr
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ENTRY(sa1_cache_purgeD_E)
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mcr p15, 0, r0, c7, c10, 1 /* clean dcache entry */
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mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */
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mcr p15, 0, r0, c7, c6, 1 /* flush D cache single entry */
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mov pc, lr
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/*
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* Soft functions
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*/
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/* sa1_cache_syncI is identical to sa1_cache_purgeID */
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ENTRY(sa1_cache_cleanID_rng)
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ENTRY(sa1_cache_cleanD_rng)
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cmp r1, #0x4000
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bcs _C_LABEL(sa1_cache_cleanID)
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and r2, r0, #0x1f
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add r1, r1, r2
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bic r0, r0, #0x1f
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1: mcr p15, 0, r0, c7, c10, 1 /* clean D cache entry */
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add r0, r0, #32
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subs r1, r1, #32
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bhi 1b
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mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */
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mov pc, lr
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ENTRY(sa1_cache_purgeID_rng)
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cmp r1, #0x4000
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bcs _C_LABEL(sa1_cache_purgeID)
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and r2, r0, #0x1f
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add r1, r1, r2
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bic r0, r0, #0x1f
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1: mcr p15, 0, r0, c7, c10, 1 /* clean D cache entry */
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mcr p15, 0, r0, c7, c6, 1 /* flush D cache single entry */
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add r0, r0, #32
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subs r1, r1, #32
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bhi 1b
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mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */
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mcr p15, 0, r0, c7, c5, 0 /* flush I cache */
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mov pc, lr
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ENTRY(sa1_cache_purgeD_rng)
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cmp r1, #0x4000
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bcs _C_LABEL(sa1_cache_purgeD)
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and r2, r0, #0x1f
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add r1, r1, r2
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bic r0, r0, #0x1f
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1: mcr p15, 0, r0, c7, c10, 1 /* clean D cache entry */
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mcr p15, 0, r0, c7, c6, 1 /* flush D cache single entry */
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add r0, r0, #32
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subs r1, r1, #32
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bhi 1b
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mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */
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mov pc, lr
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ENTRY(sa1_cache_syncI_rng)
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cmp r1, #0x4000
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bcs _C_LABEL(sa1_cache_syncI)
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and r2, r0, #0x1f
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add r1, r1, r2
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bic r0, r0, #0x1f
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1: mcr p15, 0, r0, c7, c10, 1 /* clean D cache entry */
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add r0, r0, #32
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subs r1, r1, #32
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bhi 1b
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mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */
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mcr p15, 0, r0, c7, c5, 0 /* flush I cache */
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mov pc, lr
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/*
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* Context switch.
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*
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* These are the CPU-specific parts of the context switcher cpu_switch()
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* These functions actually perform the TTB reload.
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*/
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#if defined(CPU_SA110)
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ENTRY(sa110_context_switch)
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/*
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* CF_CACHE_PURGE_ID will *ALWAYS* be called prior to this.
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* Thus the data cache will contain only kernel data and the
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* instruction cache will contain only kernel code, and all
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* kernel mappings are shared by all processes.
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*/
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/* Write the TTB */
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mcr p15, 0, r0, c2, c0, 0
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/* If we have updated the TTB we must flush the TLB */
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mcr p15, 0, r0, c8, c7, 0 /* flush the I+D tlb */
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/* Make sure that pipeline is emptied */
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mov r0, r0
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mov r0, r0
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mov pc, lr
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#endif
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