184 lines
7.9 KiB
C
184 lines
7.9 KiB
C
/* $NetBSD: ctlreg.h,v 1.6 1994/11/20 20:52:58 deraadt Exp $ */
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/*
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* Copyright (c) 1992, 1993
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* The Regents of the University of California. All rights reserved.
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*
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* This software was developed by the Computer Systems Engineering group
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* at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
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* contributed to Berkeley.
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*
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* All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the University of
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* California, Lawrence Berkeley Laboratory.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the University of
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* California, Berkeley and its contributors.
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* 4. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* @(#)ctlreg.h 8.1 (Berkeley) 6/11/93
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*/
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/*
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* Sun-4, 4c, and 4m control registers. (includes address space definitions
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* and some registers in control space).
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*/
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/* 0x00 unused */
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/* 0x01 unused */
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#if defined(SUN4C) || defined(SUN4)
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#define ASI_CONTROL 0x02 /* cache enable, context reg, etc */
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#define ASI_SEGMAP 0x03 /* segment maps (so we can reach each pmeg) */
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#define ASI_PTE 0x04 /* PTE space (pmegs) */
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#define ASI_HWFLUSHSEG 0x05 /* hardware assisted version of FLUSHSEG */
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#define ASI_HWFLUSHPG 0x06 /* hardware assisted version of FLUSHPG */
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#define ASI_HWFLUSHCTX 0x07 /* hardware assisted version of FLUSHCTX */
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#endif
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#if defined(SUN4M)
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#define ASI_SRMMUFP 0x03 /* ref mmu flush/probe */
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#define ASI_SRMMUFP_L3 (0<<8) /* probe L3 | flush L3 PTE */
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#define ASI_SRMMUFP_L2 (1<<8) /* probe L2 | flush L2/L3 PTE/PTD's */
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#define ASI_SRMMUFP_L1 (2<<8) /* probe L1 | flush L1/L2/L3 PTE/PTD's*/
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#define ASI_SRMMUFP_L0 (3<<8) /* probe L0 | flush L0/L1/L2/L3 PTE/PTD's */
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#define ASI_SRMMUFP_LN (4<<8) /* probe all | flush all levels */
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#define ASI_SRMMU 0x04 /* ref mmu registers */
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#define ASI_SRMMUDIAG 0x06
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#endif
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#define ASI_USERI 0x08 /* I-space (user) */
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#define ASI_KERNELI 0x09 /* I-space (kernel) */
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#define ASI_USERD 0x0a /* D-space (user) */
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#define ASI_KERNELD 0x0b /* D-space (kernel) */
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#if defined(SUN4C) || defined(SUN4)
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#define ASI_FLUSHSEG 0x0c /* causes hardware to flush cache segment */
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#define ASI_FLUSHPG 0x0d /* causes hardware to flush cache page */
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#define ASI_FLUSHCTX 0x0e /* causes hardware to flush cache context */
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#endif
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#if defined(SUN4)
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#define ASI_DCACHE 0x0f /* flush data cache; not used on 4c */
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#endif
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#if defined(SUN4M)
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#define ASI_ICACHETAG 0x0c /* instruction cache tag */
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#define ASI_ICACHEDATA 0x0d /* instruction cache data */
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#define ASI_DCACHETAG 0x0e /* data cache tag */
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#define ASI_DCACHEDATA 0x0f /* data cache data */
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#define ASI_IDCACHELFP 0x10 /* ms2 only: flush i&d cache line (page) */
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#define ASI_IDCACHELFS 0x11 /* ms2 only: flush i&d cache line (seg) */
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#define ASI_IDCACHELFR 0x12 /* ms2 only: flush i&d cache line (reg) */
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#define ASI_IDCACHELFC 0x13 /* ms2 only: flush i&d cache line (ctxt) */
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#define ASI_IDCACHELFU 0x14 /* ms2 only: flush i&d cache line (user) */
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#define ASI_SRMMUTLB 0x20 /* sun ref mmu bypass, ie. direct tlb access */
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#define ASI_ICACHECLR 0x36 /* ms1 only: instruction cache flash clear */
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#define ASI_DCACHECLR 0x37 /* ms1 only: data cache clear */
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#define ASI_DCACHEDIAG 0x39 /* data cache diagnostic register access */
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#endif
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#if defined(SUN4C) || defined(SUN4)
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/* registers in the control space */
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#define AC_CONTEXT 0x30000000 /* context register (byte) */
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#define AC_SYSENABLE 0x40000000 /* system enable register (byte) */
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#define AC_CACHETAGS 0x80000000 /* cache tag base address */
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#define AC_SERIAL 0xf0000000 /* special serial port sneakiness */
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/* AC_SERIAL is not used in the kernel (it is for the PROM) */
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#endif
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#if defined(SUN4)
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#define AC_IDPROM 0x00000000 /* ID PROM */
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#define AC_DVMA_ENABLE 0x50000000 /* enable user dvma */
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#define AC_BUS_ERR 0x60000000 /* bus error register */
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#define AC_DIAG_REG 0x70000000 /* diagnostic reg */
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#define AC_DVMA_MAP 0xd0000000 /* user dvma map entries */
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#define AC_VMEINTVEC 0xe0000000 /* vme interrupt vector */
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/* XXX: does not belong here */
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#define ME_REG_IERR 0x80 /* memory err ctrl reg error intr pending bit */
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#endif
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#if defined(SUN4C)
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#define AC_SYNC_ERR 0x60000000 /* sync (memory) error reg */
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#define AC_SYNC_VA 0x60000004 /* sync error virtual addr */
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#define AC_ASYNC_ERR 0x60000008 /* async error reg */
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#define AC_ASYNC_VA 0x6000000c /* async error virtual addr */
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#define AC_CACHEDATA 0x90000000 /* cached data */
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#endif
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#if defined(SUN4C) || defined(SUN4)
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/*
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* Bits in sync error register. Reading the register clears these;
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* otherwise they accumulate. The error(s) occurred at the virtual
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* address stored in the sync error address register, and may have
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* been due to, e.g., what would usually be called a page fault.
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* Worse, the bits accumulate during instruction prefetch, so
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* various bits can be on that should be off.
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*/
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#define SER_WRITE 0x8000 /* error occurred during write */
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#define SER_INVAL 0x80 /* PTE had PG_V off */
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#define SER_PROT 0x40 /* operation violated PTE prot */
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#define SER_TIMEOUT 0x20 /* bus timeout (non-existent mem) */
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#define SER_SBUSERR 0x10 /* S-Bus bus error */
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#define SER_MEMERR 0x08 /* memory ecc/parity error */
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#define SER_SZERR 0x02 /* size error, whatever that is */
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#define SER_WATCHDOG 0x01 /* watchdog reset (never see this) */
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#define SER_BITS \
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"\20\20WRITE\10INVAL\7PROT\6TIMEOUT\5SBUSERR\4MEMERR\2SZERR\1WATCHDOG"
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/*
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* Bits in async error register (errors from DVMA or Sun-4 cache
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* writeback). The corresponding bit is also set in the sync error reg.
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*
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* A writeback invalid error means there is a bug in the PTE manager.
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*
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* The word is that the async error register does not work right.
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*/
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#define AER_WBINVAL 0x80 /* writeback found PTE without PG_V */
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#define AER_TIMEOUT 0x20 /* bus timeout */
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#define AER_DVMAERR 0x10 /* bus error during DVMA */
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#define AER_BITS "\20\10WBINVAL\6TIMEOUT\5DVMAERR"
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/*
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* Bits in system enable register.
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*/
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#define SYSEN_DVMA 0x20 /* enable dvma */
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#define SYSEN_CACHE 0x10 /* enable cache */
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#define SYSEN_RESET 0x04 /* reset the hardware */
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#endif
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#if defined(SUN4M)
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#define SRMMU_PCR 0x00000000 /* processor control register */
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#define SRMMU_CXTPTR 0x00000100 /* context table pointer register */
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#define SRMMU_CXR 0x00000200 /* context register */
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#define SRMMU_SFSTAT 0x00000300 /* syncronous fault status reg */
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#define SRMMU_SFADDR 0x00000400 /* syncronous fault address reg */
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#define SRMMU_TLBCTRL 0x00001000 /* TLB replacement control reg */
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#endif
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