192 lines
6.7 KiB
C
192 lines
6.7 KiB
C
/* $NetBSD: sbd_tr2a.h,v 1.2 2008/04/28 20:23:18 martin Exp $ */
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/*-
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* Copyright (c) 2004 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by UCHIYAMA Yasushi.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _SBD_TR2A_PRIVATE
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#error "Don't inlucde this file except for TR2A implemetation"
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#endif /* !_SBD_TR2A_PRIVATE */
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#ifndef _EWS4800MIPS_SBD_TR2A_H_
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#define _EWS4800MIPS_SBD_TR2A_H_
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/*
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* EWS4800/360 (TR2A) specific system board definition
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*/
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/*
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* [interrupt overview]
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*
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* +-----+
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* | CPU |
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* +--+--+
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* |
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* +----+----+-+--+----+----+
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* INT5 INT4 INT3 INT2 INT1 INT0
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* | | | | | |
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* +-+----+----+----+----+----+-+
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* | INTC |
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* | mask: 0xbe000008 |
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* | status: 0xbe000004 |
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* | clear: 0xbe000000 | +-------------------+
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* +-+----+----+----+----+----+-+ | APbus |
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* | | | | +----+---------+Lo |
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* CLOCK---+ | +----+---------+---------+Hi |
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* 0xbe4a0008 | | | | |
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* (0x80) +-+---------+---------+-+ +-------------------+
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* | ASObus |
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* | mask: 0xbe40a00c |
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* | status: 0xbe40a010 |
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* | DMA int:0xbe408000 |
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* +-+---------+---------+-+
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* | | |
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* 0xbe440000 ZS-+ | |
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* 0xbe480000 KBMS | |
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* | |
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* 0xbe500000 SCSI-A-------+ |
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* 0xbe510000 SCSI-B-------+ |
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* 0xbe400000 LANCE--------+ |
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* |
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* NMI-------------------------+
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*
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* [INTC interrupt mask] 0xbe000008
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* 0x80000000 INT5
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* 0x04000000 INT4
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* 0x00200000 INT3
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* 0x00010000 INT2
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* 0x00000800 INT1
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* 0x00000020 INT0
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*
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* [ASObus interrupt mask] 0xbe40a00c
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* TR2A
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* 0x00800000 INT4 -
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* 0x00400000 INT4 -
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* 0x00300010 INT4 ZS
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* 0x00000040 INT4 KBMS
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* 0x00000020 INT4 -
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* 0x00000100 INT2 simd2 A
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* 0x00000200 INT2 simd2 B
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* 0x00000001 INT2 limd2
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* 0x00008000 INT0 NMI
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* 0x00000008 INT0 -
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* 0x00000004 INT0 -
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* 0x00f0837d 0x00300351
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*/
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/* ROM */
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#define TR2A_ROM_FONT_ADDR 0xbfc0ec00
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#define TR2A_SCSIROM_ADDR 0xbfc80000
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#define TR2A_GAROM_ADDR 0xbfc82000
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#define TR2A_ROM_KEYMAP_NORMAL ((uint8_t *)0xbfc39140)
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#define TR2A_ROM_KEYMAP_SHIFTED ((uint8_t *)0xbfc38e40)
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#define TR2A_ROM_KEYMAP_CONTROL ((uint8_t *)0xbfc38ec0)
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#define TR2A_ROM_KEYMAP_CAPSLOCK ((uint8_t *)0xbfc39040)
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/* System board I/O devices */
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#define TR2A_IOBASE_ADDR 0xbe000000
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#define TR2A_LANCE_BASE 0xbe400000 /* Ether AM79C90 */
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#define TR2A_SIO_BASE 0xbe440000 /* SIO1 85230 */
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#define TR2A_KBMS_BASE 0xbe480000 /* SIO0 85230 */
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#define TR2A_NVSRAM_BASE 0xbe490000 /* NVSRAM */
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#define TR2A_SCSIA_BASE 0xbe500000 /* SCSI-A NCR53C710 */
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#define TR2A_SCSIB_BASE 0xbe510000 /* SCSI-B NCR53C710 */
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#if 0
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#define TR2A_FDC_BASE 0xbe420000
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#define TR2A_LPT_BASE 0xbe430000
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#define TR2A_APBUS_INTC_MASK 0xbe806000
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#define TR2A_VMECHK 0xbe000040
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#define TR2A_CLK 0xbe000024
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#endif
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/* APbus */
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#define TR2A_APBUS_ADDR 0xe0000000
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#define TR2A_APBUS_SIZE 0x18000000
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/* NVSRAM */
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#define TR2A_NVSRAM_ADDR 0xbe490000
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#define NVSRAM_SIGNATURE 0xbe490000
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#define NVSRAM_MACHINEID 0xbe490010
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#define NVSRAM_ETHERADDR 0xbe491008
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#define NVSRAM_TF_PROGRESS 0xbe493010
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#define NVSRAM_TF_ERROR 0xbe493028
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#define NVSRAM_BOOTDEV ((uint8_t *)0xbe493030)
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#define NVSRAM_CONSTYPE ((uint8_t *)0xbe4932a0)
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#define NVSRAM_BOOTUNIT 0xbe493414
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#define NVSRAM_SBDINIT_0 0xbe493450
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#define NVSRAM_SBDINIT_1 0xbe493454
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#define NVSRAM_SBDINIT_2 0xbe493458
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#define NVSRAM_SBDINIT_3 0xbe49345c
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/* Frame buffer */
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#define TR2A_GAFB_ADDR 0xf0000000
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#define TR2A_GAFB_SIZE 0x04000000
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#define TR2A_GAREG_ADDR 0xf5f00000
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#define TR2A_GAREG_SIZE 0x00001000
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#define SOFTRESET_REG ((volatile uint8_t *)0xba000004)
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#define SOFTRESET_FLAG ((volatile uint32_t *)0xbe000064)
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#define CLOCK_REG ((volatile uint8_t *)0xbe4a0008)
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#define POWEROFF_REG ((volatile uint8_t *)0xbe4a0030)
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#define LED_TF_REG ((volatile uint8_t *)0xbe4a0040)
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#define LED_TF_ON 1
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#define LED_TF_OFF 0
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#define TF_ERROR_CODE ((volatile uint8_t *)0xbe4a0044)
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#define BUZZER_REG ((volatile uint8_t *)0xbe4a0050)
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/* Keyboard/Mouse Z85230 */
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#define KBD_STATUS ((volatile uint8_t *)0xbe480000)
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#define KBD_DATA ((volatile uint8_t *)0xbe480004)
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/* RTC */
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#define RTC_MK48T18_ADDR ((volatile uint8_t *)0xbe493fe0)
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#define RTC_MK48T18_NVSRAM_ADDR 0xbe490000
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/* INTC */
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#define INTC_CLEAR_REG ((volatile uint32_t *)0xbe000000)
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#define INTC_STATUS_REG ((volatile uint32_t *)0xbe000004)
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#define INTC_MASK_REG ((volatile uint32_t *)0xbe000008)
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#define INTC_INT5 0x80000000
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#define INTC_INT4 0x04000000
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#define INTC_INT3 0x00200000
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#define INTC_INT2 0x00010000
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#define INTC_INT1 0x00000800
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#define INTC_INT0 0x00000020
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/* ASO */
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#define ASO_DMAINT_STATUS_REG ((volatile uint32_t *)0xbe408000)
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#define ASO_INT_MASK_REG ((volatile uint32_t *)0xbe40a00c)
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#define ASO_INT_STATUS_REG ((volatile uint32_t *)0xbe40a010)
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#define TR2A_ASO_INTMASK_ALL 0x00f0837d
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/* Graphic adapter */
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#include <machine/gareg.h>
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#endif /* !_EWS4800MIPS_SBD_TR2_H_ */
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