123 lines
3.8 KiB
C
123 lines
3.8 KiB
C
/* $NetBSD: mvphyreg.h,v 1.1 2006/07/21 23:55:27 gdamore Exp $ */
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/*-
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* Copyright (c) 2006 Sam Leffler, Errno Consulting
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/*
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* Definitions for the Marvell 88E6060 Ethernet PHY.
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*/
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#ifndef _DEV_MII_MVPHYREG_H_
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#define _DEV_MII_MVPHYREG_H_
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/*
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* PHY Registers
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*/
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#define MII_MV_PHY_SPECIFIC_STATUS 17
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#define MII_MV_SWITCH_GLOBAL_ADDR 31 /* switch itself */
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/* MV_PHY_SPECIFIC_STATUS fields */
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#define MV_STATUS_RESOLVED_SPEED_100 0x4000
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#define MV_STATUS_RESOLVED_DUPLEX_FULL 0x2000
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#define MV_STATUS_RESOLVED 0x0800
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#define MV_STATUS_REAL_TIME_LINK_UP 0x0400
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/*
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* Per-Port Switch Registers
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*/
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#define MV_PORT_STATUS 0
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#define MV_SWITCH_ID 3
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#define MV_PORT_CONTROL 4
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#define MV_PORT_BASED_VLAN_MAP 6
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#define MV_PORT_ASSOCIATION_VECTOR 11
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#define MV_RX_COUNTER 16
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#define MV_TX_COUNTER 17
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/* MV_SWITCH_ID fields */
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#define MV_SWITCH_ID_DEV 0xfff0
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#define MV_SWITCH_ID_DEV_S 4
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#define MV_SWITCH_ID_REV 0x000f
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#define MV_SWITCH_ID_REV_S 0
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/* MV_PORT_CONTROL fields */
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#define MV_PORT_CONTROL_PORT_STATE 0x0003
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#define MV_PORT_CONTROL_PORT_STATE_DISABLED 0x0000
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#define MV_PORT_CONTROL_PORT_STATE_FORWARDING 0x0003
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#define MV_PORT_CONTROL_EGRESS_MODE 0x0100 /* enable on rx */
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#define MV_PORT_CONTROL_INGRESS_TRAILER 0x4000 /* enable on tx */
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#define MV_EGRESS_TRAILER_VALID 0x80
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#define MV_INGRESS_TRAILER_OVERRIDE 0x80
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#define MV_PHY_TRAILER_SIZE 4
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/*
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* Switch Global Registers accessed via MII_MV_SWITCH_GLOBAL_ADDR.
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*/
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#define MV_SWITCH_GLOBAL_STATUS 0
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#define MV_SWITCH_MAC_ADDR0 1
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#define MV_SWITCH_MAC_ADDR2 2
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#define MV_SWITCH_MAC_ADDR4 3
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#define MV_SWITCH_GLOBAL_CONTROL 4
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#define MV_ATU_CONTROL 10
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#define MV_ATU_OPERATION 11
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#define MV_ATU_DATA 12
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#define MV_ATU_MAC_ADDR0 13
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#define MV_ATU_MAC_ADDR2 14
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#define MV_ATU_MAC_ADDR4 15
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/* MV_SWITCH_GLOBAL_STATUS fields */
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#define MV_SWITCH_STATUS_READY 0x0800
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/* MV_SWITCH_GLOBAL_CONTROL fields */
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#define MV_CTRMODE 0x0100
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#define MV_CTRMODE_GOODFRAMES 0x0000
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#define MV_CTRMODE_BADFRAMES 0x0100
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/* MV_ATU_CONTROL fields */
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#define MV_ATUCTRL_ATU_SIZE 0x3000
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#define MV_ATUCTRL_ATU_SIZE_S 12
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#define MV_ATUCTRL_AGE_TIME 0x0ff0
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#define MV_ATUCTRL_AGE_TIME_S 4
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/* MV_ATU_OPERATION fields */
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#define MV_ATU_BUSY 0x8000
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#define MV_ATU_OP 0x7000
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#define MV_ATU_OP_FLUSH_ALL 0x1000
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#define MV_ATU_OP_GET_NEXT 0x4000
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#define MV_ATU_IS_BUSY(v) (((v) & MV_ATU_BUSY) != 0)
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/* MV_ATU_DATA fields */
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#define MV_ENTRYPRI 0xc000
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#define MV_ENTRYPRI_S 14
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#define MV_PORTVEC 0x03f0
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#define MV_PORTVEC_S 4
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#define MV_ENTRYSTATE 0x000f
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#define MV_ENTRYSTATE_S 0
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#endif /* _DEV_MII_MVPHYREG_H_ */
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