583 lines
15 KiB
C
583 lines
15 KiB
C
/* $NetBSD: hpc.c,v 1.37 2006/09/01 04:47:44 sekiya Exp $ */
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/*
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* Copyright (c) 2000 Soren S. Jorvang
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* Copyright (c) 2001 Rafal K. Boni
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* Copyright (c) 2001 Jason R. Thorpe
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed for the
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* NetBSD Project. See http://www.NetBSD.org/ for
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* information about NetBSD.
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* 4. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: hpc.c,v 1.37 2006/09/01 04:47:44 sekiya Exp $");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#include <sys/device.h>
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#include <sys/reboot.h>
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#include <sys/callout.h>
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#include <machine/machtype.h>
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#include <sgimips/gio/gioreg.h>
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#include <sgimips/gio/giovar.h>
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#include <sgimips/hpc/hpcvar.h>
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#include <sgimips/hpc/hpcreg.h>
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#include <sgimips/ioc/iocreg.h>
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#include "locators.h"
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#define HPC_REVISION_MASK 0x3
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#define HPC_REVISION_1 0x1
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#define HPC_REVISION_15 0x2
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#define HPC_REVISION_3 0x3
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const struct hpc_device {
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const char *hd_name;
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bus_addr_t hd_base;
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bus_addr_t hd_devoff;
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bus_addr_t hd_dmaoff;
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int hd_irq;
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int hd_sysmask;
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} hpc_devices[] = {
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{ "zsc",
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HPC_BASE_ADDRESS_0,
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/* XXX Magic numbers */
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HPC3_PBUS_CH6_DEVREGS + IOC_SERIAL_REGS, 0,
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29,
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HPCDEV_IP22 | HPCDEV_IP24 },
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/* probe order is important for IP20 zsc */
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{ "zsc", /* serial 0/1 duart 1 */
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HPC_BASE_ADDRESS_0,
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0x0d10, 0,
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5,
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HPCDEV_IP12 | HPCDEV_IP20 },
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{ "zsc", /* kbd/ms duart 0 */
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HPC_BASE_ADDRESS_0,
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0x0d00, 0,
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5,
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HPCDEV_IP12 | HPCDEV_IP20 },
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{ "pckbc",
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HPC_BASE_ADDRESS_0,
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HPC3_PBUS_CH6_DEVREGS + IOC_KB_REGS, 0,
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28,
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HPCDEV_IP22 | HPCDEV_IP24 },
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{ "sq",
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HPC_BASE_ADDRESS_0,
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HPC3_ENET_DEVREGS, HPC3_ENET_REGS,
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3,
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HPCDEV_IP22 | HPCDEV_IP24 },
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{ "sq",
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HPC_BASE_ADDRESS_0,
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HPC1_ENET_DEVREGS, HPC1_ENET_REGS,
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3,
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HPCDEV_IP12 | HPCDEV_IP20 },
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{ "sq",
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HPC_BASE_ADDRESS_1,
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HPC1_ENET_DEVREGS, HPC1_ENET_REGS,
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6,
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HPCDEV_IP12 | HPCDEV_IP20 },
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{ "sq",
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HPC_BASE_ADDRESS_1,
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HPC1_ENET_DEVREGS, HPC1_ENET_REGS,
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22,
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HPCDEV_IP24 },
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{ "sq",
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HPC_BASE_ADDRESS_2,
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HPC1_ENET_DEVREGS, HPC1_ENET_REGS,
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15,
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HPCDEV_IP12 | HPCDEV_IP20 },
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{ "sq",
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HPC_BASE_ADDRESS_2,
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HPC1_ENET_DEVREGS, HPC1_ENET_REGS,
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23,
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HPCDEV_IP24 },
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{ "wdsc",
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HPC_BASE_ADDRESS_0,
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HPC3_SCSI0_DEVREGS, HPC3_SCSI0_REGS,
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1, /* XXX 1 = IRQ_LOCAL0 + 1 */
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HPCDEV_IP22 | HPCDEV_IP24 },
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{ "wdsc",
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HPC_BASE_ADDRESS_0,
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HPC3_SCSI1_DEVREGS, HPC3_SCSI1_REGS,
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2, /* XXX 2 = IRQ_LOCAL0 + 2 */
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HPCDEV_IP22 },
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{ "wdsc",
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HPC_BASE_ADDRESS_0,
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HPC1_SCSI0_DEVREGS, HPC1_SCSI0_REGS,
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2, /* XXX 1 = IRQ_LOCAL0 + 2 */
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HPCDEV_IP12 | HPCDEV_IP20 },
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{ "dpclock",
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HPC_BASE_ADDRESS_0,
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HPC1_PBUS_BBRAM, 0,
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-1,
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HPCDEV_IP12 | HPCDEV_IP20 },
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{ "dsclock",
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HPC_BASE_ADDRESS_0,
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HPC3_PBUS_BBRAM, 0,
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-1,
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HPCDEV_IP22 | HPCDEV_IP24 },
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{ "haltwo",
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HPC_BASE_ADDRESS_0,
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HPC3_PBUS_CH0_DEVREGS, HPC3_PBUS_DMAREGS,
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8 + 4, /* XXX IRQ_LOCAL1 + 4 */
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HPCDEV_IP22 | HPCDEV_IP24 },
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{ "pi1ppc",
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HPC_BASE_ADDRESS_0,
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HPC3_PBUS_CH6_DEVREGS + IOC_PLP_REGS, 0,
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-1,
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HPCDEV_IP22 | HPCDEV_IP24 },
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{ NULL,
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0,
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0, 0,
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0,
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0
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}
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};
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struct hpc_softc {
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struct device sc_dev;
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bus_addr_t sc_base;
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bus_space_tag_t sc_ct;
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bus_space_handle_t sc_ch;
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};
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static struct hpc_values hpc1_values = {
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.revision = 1,
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.scsi0_regs = HPC1_SCSI0_REGS,
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.scsi0_regs_size = HPC1_SCSI0_REGS_SIZE,
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.scsi0_cbp = HPC1_SCSI0_CBP,
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.scsi0_ndbp = HPC1_SCSI0_NDBP,
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.scsi0_bc = HPC1_SCSI0_BC,
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.scsi0_ctl = HPC1_SCSI0_CTL,
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.scsi0_gio = HPC1_SCSI0_GIO,
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.scsi0_dev = HPC1_SCSI0_DEV,
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.scsi0_dmacfg = HPC1_SCSI0_DMACFG,
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.scsi0_piocfg = HPC1_SCSI0_PIOCFG,
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.scsi1_regs = HPC1_SCSI1_REGS,
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.scsi1_regs_size = HPC1_SCSI1_REGS_SIZE,
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.scsi1_cbp = HPC1_SCSI1_CBP,
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.scsi1_ndbp = HPC1_SCSI1_NDBP,
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.scsi1_bc = HPC1_SCSI1_BC,
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.scsi1_ctl = HPC1_SCSI1_CTL,
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.scsi1_gio = HPC1_SCSI1_GIO,
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.scsi1_dev = HPC1_SCSI1_DEV,
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.scsi1_dmacfg = HPC1_SCSI1_DMACFG,
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.scsi1_piocfg = HPC1_SCSI1_PIOCFG,
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.dmactl_dir = HPC1_DMACTL_DIR,
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.dmactl_flush = HPC1_DMACTL_FLUSH,
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.dmactl_active = HPC1_DMACTL_ACTIVE,
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.dmactl_reset = HPC1_DMACTL_RESET,
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.enet_regs = HPC1_ENET_REGS,
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.enet_regs_size = HPC1_ENET_REGS_SIZE,
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.enet_intdelay = HPC1_ENET_INTDELAY,
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.enet_intdelayval = HPC1_ENET_INTDELAY_OFF,
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.enetr_cbp = HPC1_ENETR_CBP,
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.enetr_ndbp = HPC1_ENETR_NDBP,
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.enetr_bc = HPC1_ENETR_BC,
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.enetr_ctl = HPC1_ENETR_CTL,
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.enetr_ctl_active = HPC1_ENETR_CTL_ACTIVE,
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.enetr_reset = HPC1_ENETR_RESET,
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.enetr_dmacfg = 0,
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.enetr_piocfg = 0,
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.enetx_cbp = HPC1_ENETX_CBP,
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.enetx_ndbp = HPC1_ENETX_NDBP,
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.enetx_bc = HPC1_ENETX_BC,
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.enetx_ctl = HPC1_ENETX_CTL,
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.enetx_ctl_active = HPC1_ENETX_CTL_ACTIVE,
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.enetx_dev = 0,
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.enetr_fifo = HPC1_ENETR_FIFO,
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.enetr_fifo_size = HPC1_ENETR_FIFO_SIZE,
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.enetx_fifo = HPC1_ENETX_FIFO,
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.enetx_fifo_size = HPC1_ENETX_FIFO_SIZE,
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.scsi0_devregs_size = HPC1_SCSI0_DEVREGS_SIZE,
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.scsi1_devregs_size = HPC1_SCSI0_DEVREGS_SIZE,
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.enet_devregs = HPC1_ENET_DEVREGS,
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.enet_devregs_size = HPC1_ENET_DEVREGS_SIZE,
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.pbus_fifo = 0,
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.pbus_fifo_size = 0,
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.pbus_bbram = 0,
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#define MAX_SCSI_XFER (512*1024)
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.scsi_max_xfer = MAX_SCSI_XFER,
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.scsi_dma_segs = (MAX_SCSI_XFER / 4096),
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.scsi_dma_segs_size = 4096,
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.clk_freq = 100,
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.dma_datain_cmd = (HPC1_DMACTL_ACTIVE | HPC1_DMACTL_DIR),
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.dma_dataout_cmd = HPC1_DMACTL_ACTIVE,
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.scsi_dmactl_flush = HPC1_DMACTL_FLUSH,
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.scsi_dmactl_active = HPC1_DMACTL_ACTIVE,
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.scsi_dmactl_reset = HPC1_DMACTL_RESET
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};
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static struct hpc_values hpc3_values = {
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.revision = 3,
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.scsi0_regs = HPC3_SCSI0_REGS,
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.scsi0_regs_size = HPC3_SCSI0_REGS_SIZE,
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.scsi0_cbp = HPC3_SCSI0_CBP,
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.scsi0_ndbp = HPC3_SCSI0_NDBP,
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.scsi0_bc = HPC3_SCSI0_BC,
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.scsi0_ctl = HPC3_SCSI0_CTL,
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.scsi0_gio = HPC3_SCSI0_GIO,
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.scsi0_dev = HPC3_SCSI0_DEV,
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.scsi0_dmacfg = HPC3_SCSI0_DMACFG,
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.scsi0_piocfg = HPC3_SCSI0_PIOCFG,
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.scsi1_regs = HPC3_SCSI1_REGS,
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.scsi1_regs_size = HPC3_SCSI1_REGS_SIZE,
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.scsi1_cbp = HPC3_SCSI1_CBP,
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.scsi1_ndbp = HPC3_SCSI1_NDBP,
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.scsi1_bc = HPC3_SCSI1_BC,
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.scsi1_ctl = HPC3_SCSI1_CTL,
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.scsi1_gio = HPC3_SCSI1_GIO,
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.scsi1_dev = HPC3_SCSI1_DEV,
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.scsi1_dmacfg = HPC3_SCSI1_DMACFG,
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.scsi1_piocfg = HPC3_SCSI1_PIOCFG,
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.dmactl_dir = HPC3_DMACTL_DIR,
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.dmactl_flush = HPC3_DMACTL_FLUSH,
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.dmactl_active = HPC3_DMACTL_ACTIVE,
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.dmactl_reset = HPC3_DMACTL_RESET,
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.enet_regs = HPC3_ENET_REGS,
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.enet_regs_size = HPC3_ENET_REGS_SIZE,
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.enet_intdelay = 0,
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.enet_intdelayval = 0,
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.enetr_cbp = HPC3_ENETR_CBP,
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.enetr_ndbp = HPC3_ENETR_NDBP,
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.enetr_bc = HPC3_ENETR_BC,
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.enetr_ctl = HPC3_ENETR_CTL,
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.enetr_ctl_active = HPC3_ENETR_CTL_ACTIVE,
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.enetr_reset = HPC3_ENETR_RESET,
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.enetr_dmacfg = HPC3_ENETR_DMACFG,
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.enetr_piocfg = HPC3_ENETR_PIOCFG,
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.enetx_cbp = HPC3_ENETX_CBP,
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.enetx_ndbp = HPC3_ENETX_NDBP,
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.enetx_bc = HPC3_ENETX_BC,
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.enetx_ctl = HPC3_ENETX_CTL,
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.enetx_ctl_active = HPC3_ENETX_CTL_ACTIVE,
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.enetx_dev = HPC3_ENETX_DEV,
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.enetr_fifo = HPC3_ENETR_FIFO,
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.enetr_fifo_size = HPC3_ENETR_FIFO_SIZE,
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.enetx_fifo = HPC3_ENETX_FIFO,
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.enetx_fifo_size = HPC3_ENETX_FIFO_SIZE,
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.scsi0_devregs_size = HPC3_SCSI0_DEVREGS_SIZE,
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.scsi1_devregs_size = HPC3_SCSI1_DEVREGS_SIZE,
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.enet_devregs = HPC3_ENET_DEVREGS,
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.enet_devregs_size = HPC3_ENET_DEVREGS_SIZE,
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.pbus_fifo = HPC3_PBUS_FIFO,
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.pbus_fifo_size = HPC3_PBUS_FIFO_SIZE,
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.pbus_bbram = HPC3_PBUS_BBRAM,
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.scsi_max_xfer = MAX_SCSI_XFER,
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.scsi_dma_segs = (MAX_SCSI_XFER / 8192),
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.scsi_dma_segs_size = 8192,
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.clk_freq = 100,
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.dma_datain_cmd = HPC3_DMACTL_ACTIVE,
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.dma_dataout_cmd = (HPC3_DMACTL_ACTIVE | HPC3_DMACTL_DIR),
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.scsi_dmactl_flush = HPC3_DMACTL_FLUSH,
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.scsi_dmactl_active = HPC3_DMACTL_ACTIVE,
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.scsi_dmactl_reset = HPC3_DMACTL_RESET
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};
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extern int mach_type; /* IPxx type */
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extern int mach_subtype; /* subtype: eg., Guiness/Fullhouse for IP22 */
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extern int mach_boardrev; /* machine board revision, in case it matters */
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extern struct sgimips_bus_dma_tag sgimips_default_bus_dma_tag;
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static int powerintr_established;
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int hpc_match(struct device *, struct cfdata *, void *);
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void hpc_attach(struct device *, struct device *, void *);
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int hpc_print(void *, const char *);
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int hpc_revision(struct hpc_softc *, struct gio_attach_args *);
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int hpc_submatch(struct device *, struct cfdata *,
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const int *, void *);
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int hpc_power_intr(void *);
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#if defined(BLINK)
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static struct callout hpc_blink_ch = CALLOUT_INITIALIZER;
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static void hpc_blink(void *);
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#endif
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CFATTACH_DECL(hpc, sizeof(struct hpc_softc),
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hpc_match, hpc_attach, NULL, NULL);
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int
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hpc_match(struct device *parent, struct cfdata *cf, void *aux)
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{
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struct gio_attach_args* ga = aux;
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/* Make sure it's actually there and readable */
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if (badaddr((void*)MIPS_PHYS_TO_KSEG1(ga->ga_addr), sizeof(u_int32_t)))
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return 0;
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return 1;
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}
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void
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hpc_attach(struct device *parent, struct device *self, void *aux)
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{
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struct hpc_softc *sc = (struct hpc_softc *)self;
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struct gio_attach_args* ga = aux;
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struct hpc_attach_args ha;
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const struct hpc_device *hd;
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uint32_t hpctype;
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int sysmask;
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switch (mach_type) {
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case MACH_SGI_IP12:
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sysmask = HPCDEV_IP12;
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break;
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case MACH_SGI_IP20:
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sysmask = HPCDEV_IP20;
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break;
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case MACH_SGI_IP22:
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if (mach_subtype == MACH_SGI_IP22_FULLHOUSE)
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sysmask = HPCDEV_IP22;
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else
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sysmask = HPCDEV_IP24;
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break;
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default:
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panic("hpc_attach: can't handle HPC on an IP%d", mach_type);
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};
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if ((hpctype = hpc_revision(sc, ga)) == 0)
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panic("hpc_attach: could not identify HPC revision\n");
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/* force big-endian mode */
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if (hpctype == 15)
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*(uint32_t *)MIPS_PHYS_TO_KSEG1(ga->ga_addr+HPC1_BIGENDIAN) = 0;
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printf(": SGI HPC%d%s\n", (hpctype == 3) ? 3 : 1,
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(hpctype == 15) ? ".5" : "");
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sc->sc_ct = 1;
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sc->sc_ch = ga->ga_ioh;
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sc->sc_base = ga->ga_addr;
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for (hd = hpc_devices; hd->hd_name != NULL; hd++) {
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if (!(hd->hd_sysmask & sysmask) || hd->hd_base != sc->sc_base)
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continue;
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ha.ha_name = hd->hd_name;
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ha.ha_devoff = hd->hd_devoff;
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ha.ha_dmaoff = hd->hd_dmaoff;
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ha.ha_irq = hd->hd_irq;
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/* XXX This is disgusting. */
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ha.ha_st = 1;
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ha.ha_sh = MIPS_PHYS_TO_KSEG1(sc->sc_base);
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ha.ha_dmat = &sgimips_default_bus_dma_tag;
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if (hpctype == 3)
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ha.hpc_regs = &hpc3_values;
|
|
else
|
|
ha.hpc_regs = &hpc1_values;
|
|
ha.hpc_regs->revision = hpctype;
|
|
|
|
(void) config_found_sm_loc(self, "hpc", NULL, &ha, hpc_print,
|
|
hpc_submatch);
|
|
}
|
|
|
|
/*
|
|
* XXX: Only attach the powerfail interrupt once, since the
|
|
* interrupt code doesn't let you share interrupt just yet.
|
|
*
|
|
* Since the powerfail interrupt is hardcoded to read from
|
|
* a specific register anyway (XXX#2!), we don't care when
|
|
* it gets attached, as long as it only happens once.
|
|
*/
|
|
if (mach_type == MACH_SGI_IP22 && !powerintr_established) {
|
|
cpu_intr_establish(9, IPL_NONE, hpc_power_intr, sc);
|
|
powerintr_established++;
|
|
}
|
|
|
|
#if defined(BLINK)
|
|
if (mach_type == MACH_SGI_IP12 || mach_type == MACH_SGI_IP20)
|
|
hpc_blink(sc);
|
|
#endif
|
|
}
|
|
|
|
int
|
|
hpc_revision(struct hpc_softc *sc, struct gio_attach_args *ga)
|
|
{
|
|
int hpctype;
|
|
|
|
/* Allow forcing of our hpc revision. */
|
|
switch (device_cfdata(&sc->sc_dev)->cf_flags & HPC_REVISION_MASK) {
|
|
case HPC_REVISION_1:
|
|
return (1);
|
|
|
|
case HPC_REVISION_15:
|
|
return (15);
|
|
|
|
case HPC_REVISION_3:
|
|
return (3);
|
|
}
|
|
|
|
/* XXX We should really come up with an autodetect mechanism */
|
|
switch (mach_type) {
|
|
case MACH_SGI_IP12:
|
|
hpctype = 1;
|
|
break;
|
|
|
|
case MACH_SGI_IP20:
|
|
hpctype = 15;
|
|
break;
|
|
|
|
case MACH_SGI_IP22:
|
|
hpctype = 3;
|
|
break;
|
|
|
|
default:
|
|
return (0);
|
|
}
|
|
|
|
/*
|
|
* Verify HPC1 or HPC1.5
|
|
*
|
|
* For some reason the endian register isn't mapped on all
|
|
* machines (HPC1 machines?).
|
|
*/
|
|
if (hpctype == 1 || hpctype == 15) {
|
|
u_int32_t reg;
|
|
|
|
if (!badaddr((void *)MIPS_PHYS_TO_KSEG1(ga->ga_addr +
|
|
HPC1_BIGENDIAN), 4)) {
|
|
reg = *(uint32_t *)MIPS_PHYS_TO_KSEG1(ga->ga_addr +
|
|
HPC1_BIGENDIAN);
|
|
|
|
if (((reg >> HPC1_REVSHIFT) & HPC1_REVMASK) ==
|
|
HPC1_REV15)
|
|
hpctype = 15;
|
|
else
|
|
hpctype = 1;
|
|
} else
|
|
hpctype = 1;
|
|
}
|
|
|
|
return (hpctype);
|
|
}
|
|
|
|
int
|
|
hpc_submatch(struct device *parent, struct cfdata *cf,
|
|
const int *ldesc, void *aux)
|
|
{
|
|
struct hpc_attach_args *ha = aux;
|
|
|
|
if (cf->cf_loc[HPCCF_OFFSET] != HPCCF_OFFSET_DEFAULT &&
|
|
(bus_addr_t) cf->cf_loc[HPCCF_OFFSET] != ha->ha_devoff)
|
|
return (0);
|
|
|
|
return (config_match(parent, cf, aux));
|
|
}
|
|
|
|
int
|
|
hpc_print(void *aux, const char *pnp)
|
|
{
|
|
struct hpc_attach_args *ha = aux;
|
|
|
|
if (pnp)
|
|
printf("%s at %s", ha->ha_name, pnp);
|
|
|
|
printf(" offset 0x%lx", ha->ha_devoff);
|
|
|
|
return (UNCONF);
|
|
}
|
|
|
|
int
|
|
hpc_power_intr(void *arg)
|
|
{
|
|
u_int32_t pwr_reg;
|
|
|
|
pwr_reg = *((volatile u_int32_t *)MIPS_PHYS_TO_KSEG1(0x1fbd9850));
|
|
*((volatile u_int32_t *)MIPS_PHYS_TO_KSEG1(0x1fbd9850)) = pwr_reg;
|
|
|
|
printf("hpc_power_intr: panel reg = %08x\n", pwr_reg);
|
|
|
|
if (pwr_reg & 2)
|
|
cpu_reboot(RB_HALT, NULL);
|
|
|
|
return 1;
|
|
}
|
|
|
|
#if defined(BLINK)
|
|
static void
|
|
hpc_blink(void *self)
|
|
{
|
|
struct hpc_softc *sc = (struct hpc_softc *) self;
|
|
register int s;
|
|
int value;
|
|
|
|
s = splhigh();
|
|
|
|
value = *(volatile u_int32_t *)MIPS_PHYS_TO_KSEG1(HPC1_AUX_REGS);
|
|
value ^= HPC1_AUX_CONSLED;
|
|
*(volatile u_int32_t *)MIPS_PHYS_TO_KSEG1(HPC1_AUX_REGS) = value;
|
|
splx(s);
|
|
|
|
/*
|
|
* Blink rate is:
|
|
* full cycle every second if completely idle (loadav = 0)
|
|
* full cycle every 2 seconds if loadav = 1
|
|
* full cycle every 3 seconds if loadav = 2
|
|
* etc.
|
|
*/
|
|
s = (((averunnable.ldavg[0] + FSCALE) * hz) >> (FSHIFT + 1));
|
|
callout_reset(&hpc_blink_ch, s, hpc_blink, sc);
|
|
}
|
|
#endif
|
|
|