137 lines
5.9 KiB
C
137 lines
5.9 KiB
C
/* $NetBSD: sioreg.h,v 1.1 2000/01/05 08:48:55 nisimura Exp $ */
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/*
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* Copyright (c) 1992 OMRON Corporation.
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* Copyright (c) 1992, 1993
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* The Regents of the University of California. All rights reserved.
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*
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* This code is derived from software contributed to Berkeley by
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* OMRON Corporation.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the University of
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* California, Berkeley and its contributors.
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* 4. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* @(#)sioreg.h 8.1 (Berkeley) 6/10/93
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*/
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#define WR0 0x00
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#define WR1 0x01
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#define WR2 0x02
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#define WR3 0x03
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#define WR4 0x04
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#define WR5 0x05
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#define WR6 0x06
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#define WR7 0x07
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#define WR2A WR2
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#define WR2B (WR2|0x10)
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#define RR0 0x08
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#define RR1 0x09
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#define RR2 0x0A
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#define RR3 0x0B
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#define RR4 0x0C
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#define RR2A RR2
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#define RR2B (RR2|0x10)
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#define WR0_NOP 0x00 /* No Operation */
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#define WR0_SNDABRT 0x08 /* Send Abort (HDLC) */
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#define WR0_RSTINT 0x10 /* Reset External/Status Interrupt */
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#define WR0_CHANRST 0x18 /* Channel Reset */
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#define WR0_INTNXT 0x20 /* Enable Interrupt on Next Receive Character */
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#define WR0_RSTPEND 0x28 /* Reset Transmitter Interrput/DMA Pending */
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#define WR0_ERRRST 0x30 /* Error Reset */
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#define WR0_ENDINTR 0x38 /* End of Interrupt */
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#define WR1_ESENBL 0x01 /* External/Status Interrupt Enable */
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#define WR1_TXENBL 0x02 /* Tx Interrupt/DMA Enable */
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#define WR1_STATVEC 0x04 /* Status Affects Vector (Only Chan-B) */
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#define WR1_RXDSEBL 0x00 /* Rx Interrupt/DMA Disable */
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#define WR1_RXFIRST 0x08 /* Interrupt only First Character Received */
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#define WR1_RXALLS 0x10 /* Interrupt Every Characters Received (with Special Char.) */
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#define WR1_RXALL 0x18 /* Interrupt Every Characters Received (without Special Char.) */
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#define WR2_INTR_0 0x00 /* Interrupt Priority: RxA TxA RxB TxB E/SA E/SA */
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#define WR2_INTR_1 0x04 /* Interrupt Priority: RxA RxB TxA TxB E/SA E/SA */
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#define WR2_VEC85_1 0x00 /* 8085 Vectored Mode - 1 */
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#define WR2_VEC85_2 0x08 /* 8085 Vectored Mode - 2 */
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#define WR2_VEC86 0x10 /* 8086 Vectored */
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#define WR2_VEC85_3 0x18 /* 8085 Vectored Mode - 3 */
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#define WR3_RXENBL 0x01 /* Rx Enable */
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#define WR3_RXCRC 0x08 /* Rx CRC Check */
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#define WR3_AUTOEBL 0x20 /* Auto Enable (flow control for MODEM) */
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#define WR3_RX5BIT 0x00 /* Rx Bits/Character: 5 Bits */
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#define WR3_RX7BIT 0x40 /* Rx Bits/Character: 7 Bits */
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#define WR3_RX6BIT 0x80 /* Rx Bits/Character: 6 Bits */
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#define WR3_RX8BIT 0xc0 /* Rx Bits/Character: 8 Bits */
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#define WR4_NPARITY 0x00 /* No Parity */
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#define WR4_PARENAB 0x01 /* Parity Enable */
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#define WR4_OPARITY 0x01 /* Parity Odd */
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#define WR4_EPARITY 0x02 /* Parity Even */
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#define WR4_STOP1 0x04 /* Stop Bits (1bit) */
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#define WR4_STOP15 0x08 /* Stop Bits (1.5bit) */
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#define WR4_STOP2 0x0c /* Stop Bits (2bit) */
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#define WR4_BAUD96 0x40 /* Clock Rate (9600 BAUD) */
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#define WR4_BAUD48 0x80 /* Clock Rate (4800 BAUD) */
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#define WR4_BAUD24 0xc0 /* Clock Rate (2400 BAUD) */
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#define WR5_TXCRC 0x01 /* Tx CRC Check */
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#define WR5_RTS 0x02 /* Request To Send [RTS] */
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#define WR5_TXENBL 0x08 /* Transmit Enable */
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#define WR5_BREAK 0x10 /* Send Break [BRK] */
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#define WR5_TX5BIT 0x00 /* Tx Bits/Character: 5 Bits */
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#define WR5_TX7BIT 0x20 /* Tx Bits/Character: 7 Bits */
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#define WR5_TX6BIT 0x40 /* Tx Bits/Character: 6 Bits */
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#define WR5_TX8BIT 0x60 /* Tx Bits/Character: 8 Bits */
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#define WR5_DTR 0x80 /* Data Terminal Ready [DTR] */
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#define RR0_RXAVAIL 0x01 /* Rx Character Available */
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#define RR0_INTRPEND 0x02 /* Interrupt Pending (Channel-A Only) */
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#define RR0_TXEMPTY 0x04 /* Tx Buffer Empty */
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#define RR0_DCD 0x08 /* Data Carrier Detect [DCD] */
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#define RR0_SYNC 0x10 /* Synchronization */
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#define RR0_CTS 0x20 /* Clear To Send [CTS] */
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#define RR0_BREAK 0x80 /* Break Detected [BRK] */
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#define RR1_PARITY 0x10 /* Parity Error */
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#define RR1_OVERRUN 0x20 /* Data Over Run */
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#define RR1_FRAMING 0x40 /* Framing Error */
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#define RR_RXRDY 0x0100 /* Rx Character Available */
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#define RR_INTRPEND 0x0200 /* Interrupt Pending (Channel-A Only) */
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#define RR_TXRDY 0x0400 /* Tx Buffer Empty */
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#define RR_DCD 0x0800 /* Data Carrier Detect [DCD] */
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#define RR_SYNC 0x1000 /* Synchronization */
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#define RR_CTS 0x2000 /* Clear To Send [CTS] */
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#define RR_BREAK 0x8000 /* Break Detected */
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#define RR_PARITY 0x0010 /* Parity Error */
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#define RR_OVERRUN 0x0020 /* Data Over Run */
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#define RR_FRAMING 0x0040 /* Framing Error */
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