152 lines
6.1 KiB
C
152 lines
6.1 KiB
C
/* $NetBSD: dma.h,v 1.2 1996/07/16 23:24:11 thorpej Exp $ */
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/*-
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* Copyright (c) 1992, 1993
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* The Regents of the University of California. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the University of
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* California, Berkeley and its contributors.
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* 4. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* from: @(#)dma.h 8.1 (Berkeley) 6/10/93
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*/
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/*
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* The PICA system has four dma channels capable of scatter/gather
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* and full memory addressing. The maximum transfer length is 1Mb.
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* Dma snopes the L2 cache so no precaution is required. However
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* if L1 cache is cached 'write back' the processor is responible
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* for flushing/invalidating it.
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*
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* The dma mapper has up to 4096 page descriptors.
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*/
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#define PICA_TL_BASE 0xa0008000 /* Base of tl register area */
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#define PICA_TL_SIZE 0x00008000 /* Size of tl register area */
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/*
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* Hardware dma registers.
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*/
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typedef volatile struct {
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int dma_mode;
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int pad1;
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int dma_enab;
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int pad2;
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int dma_count;
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int pad3;
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vm_offset_t dma_addr;
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int pad4;
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} DmaReg, *pDmaReg;
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#define PICA_DMA_MODE_40NS 0x00 /* Device dma timing */
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#define PICA_DMA_MODE_80NS 0x01 /* Device dma timing */
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#define PICA_DMA_MODE_120NS 0x02 /* Device dma timing */
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#define PICA_DMA_MODE_160NS 0x03 /* Device dma timing */
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#define PICA_DMA_MODE_200NS 0x04 /* Device dma timing */
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#define PICA_DMA_MODE_240NS 0x05 /* Device dma timing */
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#define PICA_DMA_MODE_280NS 0x06 /* Device dma timing */
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#define PICA_DMA_MODE_320NS 0x07 /* Device dma timing */
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#define PICA_DMA_MODE_8 0x08 /* Device 8 bit */
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#define PICA_DMA_MODE_16 0x10 /* Device 16 bit */
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#define PICA_DMA_MODE_32 0x18 /* Device 32 bit */
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#define PICA_DMA_MODE_INT 0x20 /* Interrupt when done */
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#define PICA_DMA_MODE_BURST 0x40 /* Burst mode (Rev 2 only) */
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#define PICA_DMA_MODE_FAST 0x80 /* Fast dma cycle (Rev 2 only) */
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#define PICA_DMA_MODE 0xff /* Mode register bits */
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#define DMA_DIR_WRITE 0x100 /* Software direction status */
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#define DMA_DIR_READ 0x000 /* Software direction status */
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#define PICA_DMA_ENAB_RUN 0x01 /* Enable dma */
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#define PICA_DMA_ENAB_READ 0x00 /* Read from device */
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#define PICA_DMA_ENAB_WRITE 0x02 /* Write to device */
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#define PICA_DMA_ENAB_TC_IE 0x100 /* Terminal count int enable */
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#define PICA_DMA_ENAB_ME_IE 0x200 /* Memory error int enable */
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#define PICA_DMA_ENAB_TL_IE 0x400 /* Translation limit int enable */
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#define PICA_DMA_COUNT_MASK 0x00fffff /* Byte count mask */
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#define PICA_DMA_PAGE_NUM 0xffff000 /* Address page number */
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#define PICA_DMA_PAGE_OFFS 0x0000fff /* Address page offset */
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#define PICA_DMA_PAGE_SIZE 0x0001000 /* Address page size */
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/*
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* Dma TLB entry
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*/
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typedef union dma_pte {
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struct {
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vm_offset_t lo_addr; /* Low part of translation addr */
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vm_offset_t hi_addr; /* High part of translation addr */
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} entry;
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struct bbb {
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union dma_pte *next; /* Next free translation entry */
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int size; /* Number of consecutive free entrys */
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} queue;
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} dma_pte_t;
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/*
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* Structure used to control dma.
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*/
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typedef struct dma_softc {
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struct device sc_dev; /* use as a device */
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struct esp_softc *sc_esp;
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vm_offset_t dma_va; /* Viritual address for transfer */
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int req_va; /* Original request va */
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vm_offset_t next_va; /* Value to program into dma regs */
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int next_size; /* Value to program into dma regs */
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int mode; /* Mode register value and direction */
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dma_pte_t *pte_base; /* Pointer to dma tlb array */
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int pte_size; /* Size of pte allocated pte array */
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pDmaReg dma_reg; /* Pointer to dma registers */
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int sc_active; /* Active flag */
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char **sc_dmaaddr; /* Pointer to dma address in dev */
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int *sc_dmalen; /* Pointer to len counter in dev */
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void (*reset)(struct dma_softc *); /* Reset routine pointer */
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void (*enintr)(struct dma_softc *); /* Int enab routine pointer */
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void (*map)(struct dma_softc *, caddr_t, size_t, int);
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/* Map a dma viritual area */
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void (*start)(struct dma_softc *, caddr_t, size_t, int);
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/* Start routine pointer */
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int (*isintr)(struct dma_softc *); /* Int check routine pointer */
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int (*intr)(struct dma_softc *); /* Interrupt routine pointer */
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int (*end)(struct dma_softc *); /* Interrupt routine pointer */
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} dma_softc_t;
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#define DMA_TO_DEV 0
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#define DMA_FROM_DEV 1
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#define dma_page_offs(x) ((int)(x) & PICA_DMA_PAGE_OFFS)
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#define dma_page_round(x) (((int)(x) + PICA_DMA_PAGE_OFFS) & PICA_DMA_PAGE_NUM)
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#define DMA_RESET(r) ((r->reset)(r))
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#define DMA_START(a, b, c, d) ((a->start)(a, b, c, d))
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#define DMA_MAP(a, b, c, d) ((a->map)(a, b, c, d))
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#define DMA_INTR(r) ((r->intr)(r))
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#define DMA_DRAIN(r)
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#define DMA_END(r) ((r->end)(r))
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