155 lines
4.9 KiB
C
155 lines
4.9 KiB
C
/* $NetBSD: vidcreg.h,v 1.2 2001/01/12 00:12:38 bjh21 Exp $ */
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/*-
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* Copyright (c) 1998, 2001 Ben Harris
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/* This file is part of NetBSD/arm26 -- a port of NetBSD to ARM2/3 machines. */
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/*
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* vidcreg.h - Acorn/ARM VIDC (Arabella) registers
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*/
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#ifndef _ARM26_VIDCREG_H
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#define _ARM26_VIDCREG_H
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/*
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* The VIDC is accessed by writing words to addresses starting at
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* MEMC_VIDC_BASE definied in memcreg.h.
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*
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* As with the MEMC, the value is the logical OR of the register
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* specifier and the new value.
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*/
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/* Palette entries */
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#define VIDC_PALETTE 0x00000000
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#define VIDC_PALETTE_LCOL(n) (n << 26)
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#define VIDC_PALETTE_BCOL 0x40000000
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#define VIDC_PALETTE_CCOL(n) (0x40000000 + (n << 26))
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#define VIDC_PALETTE_ENTRY(r, g, b, s) ((s != 0) << 12 | b << 8 | g << 4 | r)
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/* Stereo image registers */
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/* They're in the order 70123456 */
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#define VIDC_SIR(n) (0x60000000 + ((n + 1) % 8 << 26))
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#define VIDC_STEREO_L100 1
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#define VIDC_STEREO_L83 2
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#define VIDC_STEREO_L67 3
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#define VIDC_STEREO_C 4
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#define VIDC_STEREO_R67 5
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#define VIDC_STEREO_R83 6
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#define VIDC_STEREO_R100 7
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/* Video timing register */
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#define VIDC_HCR 0x80000000
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#define VIDC_HSWR 0x84000000
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#define VIDC_HBSR 0x88000000
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#define VIDC_HDSR 0x8c000000
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#define VIDC_HDER 0x90000000
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#define VIDC_HBER 0x94000000
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#define VIDC_HCSR 0x98000000
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#define VIDC_HIR 0x9c000000
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#define VIDC_VCR 0xa0000000
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#define VIDC_VSWR 0xa4000000
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#define VIDC_VBSR 0xa8000000
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#define VIDC_VDSR 0xac000000
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#define VIDC_VDER 0xb0000000
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#define VIDC_VBER 0xb4000000
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#define VIDC_VCSR 0xb8000000
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#define VIDC_VCER 0xbc000000
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/*
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* Horizontal timings have units of two pixels (except HCSR).
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* Vertical timings have units of a raster. Most have to have one or
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* two subtracted from them.
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*/
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#define VIDC_VIDTIMING(x) (x << 14)
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#define VIDC_HCS(x) (x << 13)
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#define VIDC_HCS_HIRES(x) (x << 11)
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/* Sound frequency register */
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#define VIDC_SFR 0xc0000000
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/* Units are us */
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#define VIDC_SF(x) (x & 0x100)
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/* Control register */
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#define VIDC_CONTROL 0xe0000000
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#define VIDC_CTL_DOTCLOCK_MASK 0x00000003
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#define VIDC_CTL_DOTCLOCK_8MHZ 0x00000000
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#define VIDC_CTL_DOTCLOCK_12MHZ 0x00000001
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#define VIDC_CTL_DOTCLOCK_16MHZ 0x00000002
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#define VIDC_CTL_DOTCLOCK_24MHZ 0x00000003
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#define VIDC_CTL_BPP_MASK 0x0000000c
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#define VIDC_CTL_BPP_ONE 0x00000000
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#define VIDC_CTL_BPP_TWO 0x00000004
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#define VIDC_CTL_BPP_FOUR 0x00000008
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#define VIDC_CTL_BPP_EIGHT 0x0000000c
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#define VIDC_CTL_DMARQ_MASK 0x00000030
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#define VIDC_CTL_DMARQ_04 0x00000000
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#define VIDC_CTL_DMARQ_15 0x00000010
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#define VIDC_CTL_DMARQ_26 0x00000020
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#define VIDC_CTL_DMARQ_37 0x00000030
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#define VIDC_CTL_INTERLACE 0x00000040
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#define VIDC_CTL_CSYNC 0x00000080
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#define VIDC_CTL_TEST_MASK 0x0000c100
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#define VIDC_CTL_TEST_OFF 0x00000000
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#define VIDC_CTL_TEST_MODE0 0x00004000
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#define VIDC_CTL_TEST_MODE1 0x00008000
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#define VIDC_CTL_TEST_MODE2 0x0000c000
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#define VIDC_CTL_TEST_MODE3 0x00000100
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#define VIDC_WRITE(value) *(volatile u_int32_t *)MEMC_VIDC_BASE = value
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/*
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* VIDC audio format is mu-law, but with the bits in a strange order.
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*
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* VIDC1 has:
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* D[7] sign
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* D[6:4] chord select
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* D[3:0] point on chord
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* so 0x00 -> +0, 0x7f -> +inf, 0x80 -> -0, 0xff -> -inf
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*
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* VIDC2 has:
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* D[7:5] chord select
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* D[4:1] point on chord
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* D[0] sign
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* so 0x00 -> +0, 0xfe -> +inf, 0x01 -> -0, 0xff -> -inf
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*
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* Normal mu-law appears to have:
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* 0x00 -> -inf, 0x7f -> -0, 0x80 -> +inf, 0xff -> +0
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* Thus VIDC1 is NOT(mu-law), while VIDC2 is NOT(mu-law)<<1 | NOT(mu-law)>>7.
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*
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* I think the A500 uses VIDC1 and the Archimedes uses VIDC2.
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*/
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#endif
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