169 lines
4.6 KiB
C
169 lines
4.6 KiB
C
/* $NetBSD: s3c2800_intr.c,v 1.1 2002/11/20 17:52:50 bsh Exp $ */
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/*
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* Copyright (c) 2002 Fujitsu Component Limited
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* Copyright (c) 2002 Genetec Corporation
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of The Fujitsu Component Limited nor the name of
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* Genetec corporation may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY FUJITSU COMPONENT LIMITED AND GENETEC
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* CORPORATION ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES,
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* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL FUJITSU COMPONENT LIMITED OR GENETEC
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* CORPORATION BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
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* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
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* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/*
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* IRQ handler for Samsung S3C2800 processor.
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* It has integrated interrupt controller.
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*/
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/malloc.h>
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#include <uvm/uvm_extern.h>
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#include <machine/bus.h>
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#include <machine/intr.h>
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#include <arm/cpufunc.h>
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#include <arm/s3c2xx0/s3c2800reg.h>
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#include <arm/s3c2xx0/s3c2800var.h>
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#include <arm/s3c2xx0/s3c2xx0_intr.h>
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/*
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* interrupt dispatch table.
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*/
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struct s3c2xx0_intr_dispatch handler[ICU_LEN];
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__volatile int softint_pending;
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__volatile int current_spl_level;
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__volatile int intr_mask;
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/* interrupt masks for each level */
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int s3c2xx0_imask[NIPL];
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int s3c2xx0_ilevel[ICU_LEN];
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int current_intr_depth;
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vaddr_t intctl_base; /* interrupt controller registers */
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#define icreg(offset) \
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(*(volatile uint32_t *)(intctl_base+(offset)))
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/*
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* Map a software interrupt queue to an interrupt priority level.
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*/
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static const int si_to_ipl[SI_NQUEUES] = {
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IPL_SOFT, /* SI_SOFT */
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IPL_SOFTCLOCK, /* SI_SOFTCLOCK */
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IPL_SOFTNET, /* SI_SOFTNET */
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IPL_SOFTSERIAL, /* SI_SOFTSERIAL */
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};
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/*
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* called from irq_entry.
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*/
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void s3c2800_irq_handler(struct clockframe *);
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void
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s3c2800_irq_handler(struct clockframe *frame)
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{
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uint32_t irqbits;
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int irqno;
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int saved_spl_level;
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++current_intr_depth;
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saved_spl_level = current_spl_level;
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/* get pending IRQs */
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irqbits = icreg(INTCTL_IRQPND) & ICU_INT_HWMASK;
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for (irqno = 0; irqbits; ++irqno) {
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if ((irqbits & (1 << irqno)) == 0)
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continue;
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/* raise spl to stop interrupts of lower priorities */
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if (saved_spl_level < handler[irqno].level)
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s3c2xx0_setipl(handler[irqno].level);
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/* clear pending bit */
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icreg(INTCTL_SRCPND) = 1 << irqno;
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#ifdef notyet
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/* Enable interrupt */
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#endif
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(*handler[irqno].func) (
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handler[irqno].cookie == 0
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? frame : handler[irqno].cookie);
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#ifdef notyet
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/* Disable interrupt */
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#endif
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irqbits &= ~(1 << irqno);
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}
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/* restore spl to that was when this interrupt happen */
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s3c2xx0_setipl(saved_spl_level);
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if (softint_pending & intr_mask)
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s3c2xx0_do_pending();
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--current_intr_depth;
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}
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void *
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s3c2800_intr_establish(int irqno, int level,
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int (* func) (void *), void *cookie)
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{
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int save;
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if (irqno < 0 || irqno >= ICU_LEN)
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panic("intr_establish: bogus irq or type");
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save = disable_interrupts(I32_bit);
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handler[irqno].cookie = cookie;
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handler[irqno].func = func;
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handler[irqno].level = level;
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s3c2xx0_update_intr_masks(irqno, level);
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intr_mask = s3c2xx0_imask[current_spl_level];
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*s3c2xx0_intr_mask_reg = intr_mask;
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restore_interrupts(save);
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return (&handler[irqno]);
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}
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void
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s3c2800_intr_init(struct s3c2800_softc *sc)
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{
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intctl_base = (vaddr_t) bus_space_vaddr(sc->sc_sx.sc_iot,
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sc->sc_sx.sc_intctl_ioh);
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s3c2xx0_intr_mask_reg = (uint32_t *)(intctl_base + INTCTL_INTMSK);
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/* clear all pending interrupt */
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icreg(INTCTL_SRCPND) = 0xffffffff;
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s3c2xx0_intr_init(handler, ICU_LEN);
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}
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