eb20bbc780
that is priority is rasied. Add a new spllowersoftclock() to provide the atomic drop-to-softclock semantics that the old splsoftclock() provided, and update calls accordingly. This fixes a problem with using the "rnd" pseudo-device from within interrupt context to extract random data (e.g. from within the softnet interrupt) where doing so would incorrectly unblock interrupts (causing all sorts of lossage). XXX 4 platforms do not have priority-raising capability: newsmips, sparc, XXX sparc64, and VAX. This platforms still have this bug until their XXX spl*() functions are fixed.
151 lines
4.9 KiB
C
151 lines
4.9 KiB
C
/* $NetBSD: intr.h,v 1.7 1999/08/05 18:08:10 thorpej Exp $ */
|
|
|
|
/*-
|
|
* Copyright (c) 1996, 1997, 1999 The NetBSD Foundation, Inc.
|
|
* All rights reserved.
|
|
*
|
|
* This code is derived from software contributed to The NetBSD Foundation
|
|
* by Jason R. Thorpe.
|
|
*
|
|
* Redistribution and use in source and binary forms, with or without
|
|
* modification, are permitted provided that the following conditions
|
|
* are met:
|
|
* 1. Redistributions of source code must retain the above copyright
|
|
* notice, this list of conditions and the following disclaimer.
|
|
* 2. Redistributions in binary form must reproduce the above copyright
|
|
* notice, this list of conditions and the following disclaimer in the
|
|
* documentation and/or other materials provided with the distribution.
|
|
* 3. All advertising materials mentioning features or use of this software
|
|
* must display the following acknowledgement:
|
|
* This product includes software developed by the NetBSD
|
|
* Foundation, Inc. and its contributors.
|
|
* 4. Neither the name of The NetBSD Foundation nor the names of its
|
|
* contributors may be used to endorse or promote products derived
|
|
* from this software without specific prior written permission.
|
|
*
|
|
* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
|
|
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
|
|
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
|
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
|
|
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
|
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
|
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
|
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
|
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
|
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
|
* POSSIBILITY OF SUCH DAMAGE.
|
|
*/
|
|
|
|
#ifndef _HP300_INTR_H_
|
|
#define _HP300_INTR_H_
|
|
|
|
#include <machine/psl.h>
|
|
|
|
#ifdef _HP300_INTR_H_PRIVATE
|
|
#include <sys/queue.h>
|
|
|
|
/*
|
|
* The location and size of the autovectored interrupt portion
|
|
* of the vector table.
|
|
*/
|
|
#define ISRLOC 0x18
|
|
#define NISR 8
|
|
|
|
struct isr {
|
|
LIST_ENTRY(isr) isr_link;
|
|
int (*isr_func) __P((void *));
|
|
void *isr_arg;
|
|
int isr_ipl;
|
|
int isr_priority;
|
|
};
|
|
#endif /* _HP300_INTR_H_PRIVATE */
|
|
|
|
/*
|
|
* Interrupt "levels". These are a more abstract representation
|
|
* of interrupt levels, and do not have the same meaning as m68k
|
|
* CPU interrupt levels. They serve two purposes:
|
|
*
|
|
* - properly order ISRs in the list for that CPU ipl
|
|
* - compute CPU PSL values for the spl*() calls.
|
|
*/
|
|
#define IPL_NONE 0 /* disable only this interrupt */
|
|
#define IPL_BIO 1 /* disable block I/O interrupts */
|
|
#define IPL_NET 2 /* disable network interrupts */
|
|
#define IPL_TTY 3 /* disable terminal interrupts */
|
|
#define IPL_TTYNOBUF 4 /* IPL_TTY + higher ISR priority */
|
|
#define IPL_CLOCK 5 /* disable clock interrupts */
|
|
#define IPL_HIGH 6 /* disable all interrupts */
|
|
|
|
/*
|
|
* Convert PSL values to CPU IPLs and vice-versa.
|
|
*/
|
|
#define PSLTOIPL(x) (((x) >> 8) & 0xf)
|
|
#define IPLTOPSL(x) ((((x) & 0xf) << 8) | PSL_S)
|
|
|
|
#ifdef _KERNEL
|
|
/* spl0 requires checking for software interrupts */
|
|
|
|
/*
|
|
* This array contains the appropriate PSL_S|PSL_IPL? values
|
|
* to raise interrupt priority to the requested level.
|
|
*/
|
|
extern unsigned short hp300_ipls[];
|
|
|
|
#define HP300_IPL_SOFT 0
|
|
#define HP300_IPL_BIO 1
|
|
#define HP300_IPL_NET 2
|
|
#define HP300_IPL_TTY 3
|
|
#define HP300_IPL_IMP 4
|
|
#define HP300_IPL_CLOCK 5
|
|
#define HP300_IPL_HIGH 6
|
|
#define HP300_NIPLS 7
|
|
|
|
/* These spl calls are _not_ to be used by machine-independent code. */
|
|
#define splhil() splraise1()
|
|
#define splkbd() splhil()
|
|
|
|
/* These spl calls are used by machine-independent code. */
|
|
#define spllowersoftclock() spl1()
|
|
#define splsoft() splraise1()
|
|
#define splsoftclock() splsoft()
|
|
#define splsoftnet() splsoft()
|
|
#define splbio() _splraise(hp300_ipls[HP300_IPL_BIO])
|
|
#define splnet() _splraise(hp300_ipls[HP300_IPL_NET])
|
|
#define spltty() _splraise(hp300_ipls[HP300_IPL_TTY])
|
|
#define splimp() _splraise(hp300_ipls[HP300_IPL_IMP])
|
|
#define splclock() spl6()
|
|
#define splstatclock() splclock()
|
|
#define splhigh() spl7()
|
|
|
|
/* watch out for side effects */
|
|
#define splx(s) ((s) & PSL_IPL ? _spl((s)) : spl0())
|
|
|
|
/*
|
|
* Simulated software interrupt register.
|
|
*/
|
|
extern volatile u_int8_t ssir;
|
|
|
|
#define SIR_NET 0x01
|
|
#define SIR_CLOCK 0x02
|
|
|
|
#define siron(mask) \
|
|
__asm __volatile ( "orb %1,%0" : "=m" (ssir) : "i" ((mask)))
|
|
#define siroff(mask) \
|
|
__asm __volatile ( "andb %1,%0" : "=m" (ssir) : "ir" (~(mask)));
|
|
|
|
#define setsoftnet() siron(SIR_NET)
|
|
#define setsoftclock() siron(SIR_CLOCK)
|
|
|
|
/* locore.s */
|
|
int spl0 __P((void));
|
|
|
|
/* intr.c */
|
|
void intr_init __P((void));
|
|
void *intr_establish __P((int (*)(void *), void *, int, int));
|
|
void intr_disestablish __P((void *));
|
|
void intr_dispatch __P((int));
|
|
void intr_printlevels __P((void));
|
|
#endif /* _KERNEL */
|
|
|
|
#endif /* _HP300_INTR_H_ */
|